11 7 DFT1 ScanDesignFlow

[@智逸湯]

Thanks for Doctor Lee explanation, it is quite useful for me.

[@jyotirmoy555]

awesome explanation Sir. Do upload on other DFT topics. Thank you very much.

[@pashahassan720]

Amazingly great job. Wonderful explanation.

[@rohanvenky]

excellent, exactly what i wanted - SC reordering.Thanks

[@shiwanichadha8353]

Thanks for detailed and precise presentation.

[@dnyaneshwarsabe3524]

good explanation sir

[@ramgopal1951]

Great explanation sir. Thank you

[@08fractal]

thanks a lot for the videos, great explanation

[@Rishabh-be6uk]

Still confused in +ve & -ve FF together...can u explain with more detailed example (assuming I will never get reply from 6 yr old video)

[@cprasanth3630]

very good explanation. Can you please explain about hold time violation?

[@李建模-k8c]

basically it means the data arrives too early. please see logic design textbook.

[@zzhong40]

Thank you for your Video,I am troubled by a inout port's S1 Error of DFT compiler(Synopsys), A Tristate inout IO pad cell, Always has a S1 Error, PAD pin show ZZZ but I simulate the verilog model with the same input value ,It is not Z ,has value 1 or 0.
I tried set_dft_configuration -type bidirection -method output
But S1 always has, Could you please give me some hint of this issue.Thanks

[@mahalakshmiamujuri6137]

sir please tell about clocks driving data and how to fix it

[@priyankamurthy5364]

can anyone give the solution for the final FFT?

[@李建模-k8c]

We can add constraints to ask ATPG to avoid violation patterns.

[@mahadesharya6975]

have you authored any text book professor? i'm searching for DFT text book - James CM Li, i'm not getting

[@李建模-k8c]

you may just read the textbooks in video 1.5

[@tuongluongthanh2030]

Thanks for detailed

[@杨翔-l7u]

very helpful to my work

[@abheshekjayaswal3856]

thank you for this