Ms Nelson, thank you for this presentation. If you permit me, I'd suggest you try to read before you say what you've read, in this way, you'll make the written words yours, and the concepts will be undesrtood much better by all of us.
Manufacturing test ensures that the Chip is manufactured as it was designed, and doesn't prove that it was designed correctly. But how can one ensure that the chip is manufactured and designed correctly at the same time? Is it validation?
Depends what you mean by validation. Usually proving the correct design and correct manufacturing of a chip is split. The correct design is proved during the design phase, this is called verification. This can be done in multiple ways i.e. formal or by simulation. But when the first silicon comes from the fab, one usually is doing a post-silicon validation. Here both is checked. Is the design correct? How good is the design regarding to concrete specification parameters (for example frequency)? Which part of my design seems to be prone for manufacturing defects (co-dependency of design and manufacturing process)? But one should avoid design mistakes at the tape-out, as it is more expensive and time consuming to fix design bugs from then on. This is why verification during the design is so important.
Always talking at a single note, kept falling asleep couple times. Also, this is too fast to understand, I wish we had the script of the presentation as well.
For more information about this course, visit: www.cadence.com/content/cadence-www/global/en_US/home/training/all-courses/82125.html You can find Lab PDF and other resources regarding this course.
Next time have an engineer read the text at least, so that they can convey some meaning, not just words. The narrator could read, but I'd be damned if they knew what even one term meant. Pity, so much expertise going to waste from a vendor like cadence, because of whatever reason prevented an engineer to deliver this lecture.
![โอ้เธอช่าง... - บี้เดอะสกา ft. ต๋อง เทวัญ (Prod. by ป๋าเพชร) [Official MV]](http://i.ytimg.com/vi/zbWhiLFmVL0/mqdefault.jpg)
Ms Nelson, thank you for this presentation. If you permit me, I'd suggest you try to read before you say what you've read, in this way, you'll make the written words yours, and the concepts will be undesrtood much better by all of us.
Logic BIST overheads (additional test points, LBIST controller etc.) are huge, at least 40% more than ATPG.
Please do add the video on amba protocol (axi) with detailed explanation it would be helpful!!!!!
Manufacturing test ensures that the Chip is manufactured as it was designed, and doesn't prove that it was designed correctly. But how can one ensure that the chip is manufactured and designed correctly at the same time?
Is it validation?
Depends what you mean by validation. Usually proving the correct design and correct manufacturing of a chip is split. The correct design is proved during the design phase, this is called verification. This can be done in multiple ways i.e. formal or by simulation. But when the first silicon comes from the fab, one usually is doing a post-silicon validation. Here both is checked. Is the design correct? How good is the design regarding to concrete specification parameters (for example frequency)? Which part of my design seems to be prone for manufacturing defects (co-dependency of design and manufacturing process)? But one should avoid design mistakes at the tape-out, as it is more expensive and time consuming to fix design bugs from then on. This is why verification during the design is so important.
This is great, thanks
Always talking at a single note, kept falling asleep couple times. Also, this is too fast to understand, I wish we had the script of the presentation as well.
For more information about this course, visit:
www.cadence.com/content/cadence-www/global/en_US/home/training/all-courses/82125.html
You can find Lab PDF and other resources regarding this course.
Thank you so much, great details
is this only covering digital dft?
Quero fazer uma aliança com Maria e comprar o kit de Maria passa na frente
Next time have an engineer read the text at least, so that they can convey some meaning, not just words. The narrator could read, but I'd be damned if they knew what even one term meant. Pity, so much expertise going to waste from a vendor like cadence, because of whatever reason prevented an engineer to deliver this lecture.
I strongly disagree - this presenter seems to have a very good grasp of what they are talking about. I am getting a lot out of this video.
@@sameergauria I don't think you watched the same presentation as rest of us
sounds like AI, waste of time.
Hard Explanation! not worth watching
waste of time, monotonous