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V-Codes
India
เข้าร่วมเมื่อ 3 ต.ค. 2011
This is the official channel for V-codes, a group of blogs aimed at helping people understand more about VHDL, Verilog and in general digital design techniques.
www.vhdlguru.blogspot.com
www.verilogcodes.blogspot.com
Please subscribe to get latest updates on this channel.
www.vhdlguru.blogspot.com
www.verilogcodes.blogspot.com
Please subscribe to get latest updates on this channel.
How to use AMD Vivado's IP Catalog to create a Block RAM
Learn how to create a new project in AMD Vivado and then generate a Block RAM IP from the built in IP's provided by AMD. Also learn how you can initialize the contents of the BRAM. The testbench code is used to verify that the design is working well.
Get the testbench code from here: vhdlguru.blogspot.com/2010/10/how-to-use-coe-file-for-initializing.html
Hope this is useful for you. If you want 1 on 1 tutoring in the field of FPGA programming, get in touch with me.
00:00 Introduction
00:45 Creating a new project in AMD Vivado
02:30 Creating BRAM from IP Catalog
07:50 How to initialize the BRAM IP with coe file?
14:08 Testing the Block RAM
Link to my VHDL Blog: vhdlguru.blogspot.com/
Link to my Verilog Blog: verilogcodes.blogspot.com/
Get the testbench code from here: vhdlguru.blogspot.com/2010/10/how-to-use-coe-file-for-initializing.html
Hope this is useful for you. If you want 1 on 1 tutoring in the field of FPGA programming, get in touch with me.
00:00 Introduction
00:45 Creating a new project in AMD Vivado
02:30 Creating BRAM from IP Catalog
07:50 How to initialize the BRAM IP with coe file?
14:08 Testing the Block RAM
Link to my VHDL Blog: vhdlguru.blogspot.com/
Link to my Verilog Blog: verilogcodes.blogspot.com/
มุมมอง: 1 210
วีดีโอ
![Find out What's Wrong with this VHDL code for RAM #2 of [Test Your VHDL Coding Skills]](http://i.ytimg.com/vi/WDMIBZW3JnM/mqdefault.jpg)
![Find out What's Wrong with this VHDL code for RAM #2 of [Test Your VHDL Coding Skills]](/img/tr.png)
Find out What's Wrong with this VHDL code for RAM #2 of [Test Your VHDL Coding Skills]
มุมมอง 3032 ปีที่แล้ว
Try and see if you can correct the mistake in the VHDL code. If not, no worries. The solution to the problem is also within the video. Download the VHDL file used in this video from here: drive.google.com/drive/folders/17zekqMDcapFALyM2oiJlV3nlsxoLzTlo?usp=sharing 0:00 - Introduction 0:32 - Explanation of RAM code 3:25 - Synthesis Results 5:27 - Solution 7:30 - Synthesis Results for the Solutio...
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In this video, I want to share and explain a LUT based Sine wave generator. The code is written so that it can be easily changed to generate different frequencies. The online tool for generating Sine values: www.daycounter.com/Calculators/Sine-Generator-Calculator.phtml VHDL Sine wave generator with testbench: drive.google.com/drive/folders/1KdR6KzqRmVuGH2LHSCLFHuHQzaTgW33m?usp=sharing Link to ...
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In this video I will be sharing and explaining VHDL for a 4 bit Ripple Carry Adder and its testbench. The testbench will test the RCA for all its available inputs and check if there is an error "Automatically". Download VHDL codes from here: drive.google.com/drive/folders/1oTZdfL_nAcppFrgyEuzThCytyHwvoQJr?usp=sharing 00:00 - Introduction 00:29 - 4 bit RCA VHDL code 03:44 - Testbench 09:33 - Sim...
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The video shows what exactly it says in the title. Short and precise. Shown with the help of a very simple example for beginners to understand how it works! Download the final code from here: drive.google.com/file/d/14JJoBVwGO5jEKrLMcTg3nvTkzsm-_fAi/view?usp=sharing
![Signal not being set correctly inside a VHDL process #1 of [Test Your VHDL Coding Skills]](http://i.ytimg.com/vi/4AeqSIQwUks/mqdefault.jpg)
Signal not being set correctly inside a VHDL process #1 of [Test Your VHDL Coding Skills]
มุมมอง 8072 ปีที่แล้ว
Try and see if you can correct the error in the VHDL code. If not, no worries. The solution to the problem is also within the video. Download the VHDL file used in this video from here: drive.google.com/file/d/1HodGn0E6LHJyu3o9sn-IBsWJESAXhGHE/view?usp=sharing 0:00 - Introduction 0:31 - VHDL code snippet 1:02 - Simulation 1:22 - Solution [Sorry for the re-upload, as the first one came out weird]
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This video is an extension of the previous video, where we discussed a Digital Clock VHDL code. In this extension project I want to convert the digital clock outputs to BCD digits and then pass it to a 7 segment decoder function so as to be able to make use of the 7 segment displays on FPGA boards. I have tested the module with the help of a testbench which I have simulated in Xilinx ISE 14.7. ...
![[Part 1] Synthesizable Digital Clock with Testbench and Simulation in VHDL](http://i.ytimg.com/vi/1PiqMRXQCAw/mqdefault.jpg)
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Writing a simple Testbench in VHDL - #1 Of Testbench Series
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Simulating a VHDL/Verilog code using Modelsim SE.
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ModelSim is a very popular simulation tool among VHDL/Verilog programmers. In this video I try to show you how to compile and simulate a simple VHDL code. The method is the same even if the codes are in Verilog. I am using the free student version of Modelsim for this. VHDL Tutorial Blog: vhdlguru.blogspot.com/ Verilog Tutorial Blog: verilogcodes.blogspot.com/
Online Automatic Testbench Generator For VHDL and Simulation Using Xilinx Vivado
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How to compile and simulate a VHDL code using Xilinx ISE
how to read data from coe file
This was a great explanation video. Can you try creating a video with self checking testbench of a slightly complex module.
i have a machine code in a txt file i would like to convert it to a .coe file, do you know anything i can use to do that?
i understood very well thanks for the videos
The signal speed in my simulation needed to be modified to work. You have your clock period at 10ns and are changing your addr every 10ns but I needed several clocks for each read. It's like my BRAM device was slower, but I used the same settings as you. Could my Verilog code effect that?
oh wait a minute, my settings are different than yours, it's a 512 x 8 so has 9 address lines, that would change the timing.
I have followed your video and added the BRAM Block from the Vivado Catalog to my Verilog design. I am not doing the COE initialization, how would that work if the design was programmed to an FPGA board? It seems the COE data file needs to come from the Vivado environment, so the FPGA board will not have this.
hi. the contents of the coe file is already processed during compilation. So the generated bit file already contains the values given in the coe file.
Thank You for the nice video, but I don't understand why it generated VHDL code, was that selected somewhere that I missed? Could I select Verilog instead?
Hi, not all IP cores have the generated code in both VHDL and Verilog. The available language(s) can be seen from the IP data sheet. For this particular IP, its only available for VHDL. But it doesnt matter, you can instantiate the IP in Verilog top module too. Just keep in mind the size and name of the input and output signals of the IP.
@@VCodes OK I think I will try to do what you suggest, to use the BRAM in a verilog design. Thanks!
thank you man , i just got a project to do on a basys 3 board and i had no idea how to do such simulation ( teacher has no time to explain everything on a study by correspondence ) and i have only week or two to do a project without a board . Anyways you just saved me with that simulation guide
so glad to hear that. I do teach for a fee when there is a request. so, if things get really troublesome in the future you can always ask me for guidance.
Hii sir how can i contact you
my email is available here: vhdlguru.blogspot.com/p/contact-me_23.html
thanks
sir , can you please share the specifications ?
what do you mean by specifications?
He has kindly provided the source code on his website, you should look there. And Thanks to VCodes for his good work!
Can you please tell me whether this code can be used for Basys 3 FPGA?
it can be used. but not directly as inputs and outputs are 72 bits each. so you would need to write a wrapper to input numbers in multiple stages. and also show the output in multiple stages. like you set the switches, push a button and then change the switches and so on.
@@VCodes Can you provide me the code if possible?
I dont have the code readymade for this. but you can write up a state machine for this. if you attempt it, I can guide you through the process. but I do charge a fee for my time. send me an email if you want.
exceptional tutorial. Best I've seen. There are only 3 things to keep in mind: signal declaration before the first begin, instantiation (port mapping), then process to update in time the inputs.
Ehm why do you have the word "verilog" in the title, if it's just vhdl? This is absurd..
Thats deliberately put there because the steps involved in simulating a verilog code is not much different than vhdl. Did you try following the steps mentioned in the video?
thank you it helps so much
You're welcome!
Very helpful video
thank you for the tutorial! was very clear and easy to follow.
Thank you!
please explain the steps involved in getting the rom values from matlab
How to compute the inverse of the square root?
how i can output the sine wave in 1 output
What do you mean?
So nice thanks
Thank you!
Good one bro.. Thanks for this tutorial. How do I map these digital outputs to 12 bit parallel DAC inputs?.
how can i run Debugdb in modelsim .
with component please
I come from a software background and I am just starting with hardware development. As such, I really appreciate examples with SIMPLE logic like this (adders, counters, memories, etc. are too complex for me at this point). Thank you for this tutorial.
Sure. Hope those things you mentioned arent that complicated anymore! To people from software background I say, "Think along hardware, and not software".
plz share any contact detail sir
my email should be visible in the "about me" section or from my blog, vhdlguru.blogspot.com/
Thank you very much
Thank you
hello, thanks a lot for the explanation of the code ,can i have the ucf document?
Hi, are you able to produce a xdc file for the basys 3 based on this.
Very helpful video
Thank you so much man....
Thank you!
Thanks for the video.
Thank you!
This was a very good explanation, it helped me a lot! Greetings from germany
Thank you!
Thank you, this is very helpful.
Thank you!
This was a very good example. Could you create a VHDL self checking test-bench.
good and rare content👌👌👍
Thank You very Much..Great Explanation...
Thank you!
thank you for your code. I used it to learn
Thank you!
thank you, this was very straight forward and not overwhelming
Thank you!
I need help with VHDL assignments. I'm willing to pay for tutoring as well... kindly reach out to me if you are interested. Thank you
I wasnt available for tutoring then. Now I have started doing so. Putting this out here for anyone who is interested. Thanks for the support.
Its shows error while compiling "library unit env is not available in library std " how to resolve this?
Hi, how do you make the clock run for a fixed duration though? I have noticed that the simulation only runs for 1000ns no matter where I try to implement this.
@@VCodes Any idea how to do it for VIVADO? The simulation window doesn't open unless I run the simulation first, which means that I cannot type in the value in the required field. Also, after running the simulation, if I try to run again by typing a specified duration, it keeps on going forever until I break it.
@@VCodes Allright, thank you.
How do you save the simulation results to a text file?
thank you for ur work, it is very useful!
thanks. glad to hear that it was helpful..
What if it has 8 7 segment display?
Just ignore the two and use the rest of the six segments. What fpga board are you using?
Great Explanation! Since this is for 6-didgit seven segment display, what if it is a 2-digit seven segment display.
@@VCodes can we have code for 4 -digits display; that is for hours and minutes only.
You can just remove the instantiation for seconds 7 segments decoder and it should work. Use whatever outputs you need and ignore the rest.
Thx for this well prepared tutorial.
loooool the cow at 4:29. Full Gaurakhshak!
lol!
worked for me, thanks!
Thank you!