Writing a simple Testbench in VHDL - #1 Of Testbench Series

[@adelingt]

exceptional tutorial. Best I've seen. There are only 3 things to keep in mind: signal declaration before the first begin, instantiation (port mapping), then process to update in time the inputs.

[@nitdawg007]

This was a great explanation video. Can you try creating a video with self checking testbench of a slightly complex module.

[@dhoneybeekingdom7889]

I come from a software background and I am just starting with hardware development. As such, I really appreciate examples with SIMPLE logic like this (adders, counters, memories, etc. are too complex for me at this point). Thank you for this tutorial.

[@VCodes]

Sure. Hope those things you mentioned arent that complicated anymore! To people from software background I say, "Think along hardware, and not software".

[@pepesylvia2208]

thank you, this was very straight forward and not overwhelming

[@VCodes]

Thank you!

[@Bo6oo]

This was a very good explanation, it helped me a lot! Greetings from germany

[@VCodes]

Thank you!

[@LNguyen921]

thank you for the tutorial! was very clear and easy to follow.

[@VCodes]

Thank you!

[@yassinekhlaf2053]

thank you it helps so much

[@VCodes]

You're welcome!

[@janhorak597]

Thank you very much

[@VCodes]

Thank you