How to compile and simulate a VHDL code using Xilinx ISE

In this video, I want to show you
1)how to create a new project
2)Add VHDL codes to it.
3)compile and simulate the codes.
4)how to see internal signals in the waveform window.
I am using Xilinx ISE for this demo. The version used is 14.6. But other xilinx versions too would follow almost the same steps.

[@lavanyapadala3119]

tq so much sir

[@VCodes]

Thank you!

[@latifbal1244]

I did all of the steps. After the final step I could not see the waveforms. Since there is still seen "Elaborating...." at the middle of the screen. And it is completed and began again and again. Something is wrong. Any idea,sir?

[@TheEternity108]

Hello Sir,
may i ask when i simulate any code it show straight lines of orange color. i have to force value to c the waveform. why does it not happen automatically. I m a novice.....
Regards

[@bhaskarchauhan6314]

error i showing failed to link the design when I simulate the test bench .. how to fix it ?

[@radheradhe159]

Why port1, port2 and port3 is showing instead of a,b,c?

[@anusuyanandi1642]

can this be done using vivado hdl webpack??

[@imshady42]

great blog though! thanks

[@VCodes]

Thank you!

[@BOARDSJEEMATHS]

is this windows 10 or 7 ? bcz simulation is not shown in windows 10

[@VCodes]

this was in Windows 7.

[@sidahmedbentrad8362]

ty for your great web site and ur video; LIKE and subscribe

[@VCodes]

Thank you!

[@VasuDev-kg6uq]

3:43

[@camicar2698]

A little bad audio, mostly for no native people like me :'(

[@VCodes]

yes! I will work on that on future videos.

[@MrOwntube]

WTF DONT UNDERSTAND A SINGLE WORD

[@VCodes]

sorry. I will work on the audio in future videos.