*Summary* * *(**0:00**)* *Purpose:* The video explains an AXI-Stream Arbiter example designed to debug data streams. It combines multiple AXI-Stream inputs and outputs them to a single UART interface for monitoring. * *(**2:38**)* *Key Components:* * *AXI-Stream Snoop Ports:* Non-intrusive interfaces that allow observation of data on the AXI-Stream bus without affecting data flow. * *FIFOs (First-In, First-Out):* Buffers used to store incoming data packets from each of the four input AXI-Stream interfaces. * *Arbiter:* Logic that manages the selection and prioritization of data from the different FIFOs to send to the UART output. * *State Machine:* Controls the overall operation of the arbiter, with states like IDLE and WRITING, ensuring data is transmitted in complete packets. * *(**2:38**)* *Arbiter Logic:* The arbiter employs a priority scheme to choose which FIFO's data to send out first. In this example, FIFO 0 has the highest priority and FIFO 3 has the lowest. * *(**2:38**)* *Data Flow:* Data comes in through four AXI-Stream Snoop Ports, is stored in individual FIFOs, then the arbiter selects which FIFO to read from based on priority and data availability, finally outputting that data to a UART for debugging. * *(**6:11**)* *Important Concepts:* The video emphasizes understanding: * *AXI-Stream Handshaking:* The use of 'ready' and 'valid' signals for data transfer. * *Synchronous and Asynchronous Logic:* Different types of logic and their importance in FPGA design, especially for state machines. * *Packet Integrity:* Ensuring complete data packets are transferred without interruption. Summarized by AI model: gemini-1.5-pro-exp-0801 Cost (if I didn't use the free tier): $0.0675 Input tokens: 16454 Output tokens: 941
please keep up the good work, i just stumbled on your AXI explanat ion video and it taught me more then a year long vhdl mentor at my company (he had a lot of knowledge, but was a bad teacher)
Interesting video, the idea of axi was alien to me until yesterday when I binged your videos. I understand it more and it makes a lot more sense for how more complex FPGA designs can exist. A question I do have though, when it comes to design architecture. If we look at your microphone to udp example. If you wanted to have a programmable gain or frequency response, or anything about the design to be programmable, how would you incorporate that? My thought would be you could use registers in a memory block to hold configuration data and through the axi stream set those registers over udp. Then your microphone or other elements can read those configuration registers. Is this how it would be done or am I completely off?
It depends if you need it for timing. Usually skid buffers are added if you need to ease timing in an axi stream bus. Another cheat is to use a small AXI stream FIFO. It's not always necessary
Could you please make a tutorial on how to re-upload a .mem file after making changes to it so that we don’t need to re-generate a bitstream? Many thanks!
The block design or Altera's Platform Designer are very impressive tools to design. However, knowing that a microblaze/nios connects to an interrupt controller for example is what I still don't understand. Do you need to take a course/learn about computer architecture to understand all those blocks or do the vendors provide them. I feel like if you told me to design LED toggling, I wouldn't know which blocks to connect or how to connect them even though I know where to click on the software to access them. How would I go about that?
Hi David, I'm not taking on any more clients at the moment, but will be making more videos in my spare time. You're welcome to suggest a video idea if there's anything specific you're interested in.
@@FPGAsforBeginners I struggle with vivado.. petalux.. the mpsoc platform has alluded me. I have a good grasp on fundamentals, system Verilog, verilog, hdl, that I can do fine, hard logic coding also isnt a struggle. Its Xilinx's software stack that's always humbling me. I find myself in Quartus alot, just to avoid feeling bloated and inefficient with vivado. Could you do a fresh onboarding video? perhaps targeting an mpsoc platform, perhaps a zcu102.. A hands on with Xilinx primitives would be cool, DSP preferably. Thanks for being awesome 💖
*Summary*
* *(**0:00**)* *Purpose:* The video explains an AXI-Stream Arbiter example designed to debug data streams. It combines multiple AXI-Stream inputs and outputs them to a single UART interface for monitoring.
* *(**2:38**)* *Key Components:*
* *AXI-Stream Snoop Ports:* Non-intrusive interfaces that allow observation of data on the AXI-Stream bus without affecting data flow.
* *FIFOs (First-In, First-Out):* Buffers used to store incoming data packets from each of the four input AXI-Stream interfaces.
* *Arbiter:* Logic that manages the selection and prioritization of data from the different FIFOs to send to the UART output.
* *State Machine:* Controls the overall operation of the arbiter, with states like IDLE and WRITING, ensuring data is transmitted in complete packets.
* *(**2:38**)* *Arbiter Logic:* The arbiter employs a priority scheme to choose which FIFO's data to send out first. In this example, FIFO 0 has the highest priority and FIFO 3 has the lowest.
* *(**2:38**)* *Data Flow:* Data comes in through four AXI-Stream Snoop Ports, is stored in individual FIFOs, then the arbiter selects which FIFO to read from based on priority and data availability, finally outputting that data to a UART for debugging.
* *(**6:11**)* *Important Concepts:* The video emphasizes understanding:
* *AXI-Stream Handshaking:* The use of 'ready' and 'valid' signals for data transfer.
* *Synchronous and Asynchronous Logic:* Different types of logic and their importance in FPGA design, especially for state machines.
* *Packet Integrity:* Ensuring complete data packets are transferred without interruption.
Summarized by AI model: gemini-1.5-pro-exp-0801
Cost (if I didn't use the free tier): $0.0675
Input tokens: 16454
Output tokens: 941
please keep up the good work, i just stumbled on your AXI explanat
ion video and it taught me more then a year long vhdl mentor at my company (he had a lot of knowledge, but was a bad teacher)
❤
Hands up everyone who has a favorite state machine! 👍
Interesting video, the idea of axi was alien to me until yesterday when I binged your videos. I understand it more and it makes a lot more sense for how more complex FPGA designs can exist. A question I do have though, when it comes to design architecture. If we look at your microphone to udp example. If you wanted to have a programmable gain or frequency response, or anything about the design to be programmable, how would you incorporate that?
My thought would be you could use registers in a memory block to hold configuration data and through the axi stream set those registers over udp. Then your microphone or other elements can read those configuration registers. Is this how it would be done or am I completely off?
Really nice vid, was just struggling with this. Would be interested to learn about pipelining an axi stream without breaking the backpressure
That is essentially what the FIFO does. AXI is a very strict specification. You can't really modify it.
Another method is using skid buffers - essentially 1 deep FIFOs.
Exactly what I was going to say. Skid buffer.
Nice vid. Now i am trying to create my own AXI4 stream arbiter (axi4 stream switch) with round robin. Do i need a skid buffer inside the arbiter?
It depends if you need it for timing. Usually skid buffers are added if you need to ease timing in an axi stream bus. Another cheat is to use a small AXI stream FIFO. It's not always necessary
Can you share basic videos of explaining the inter clock and intra clock issue
Nice video
Could you please make a tutorial on how to re-upload a .mem file after making changes to it so that we don’t need to re-generate a bitstream? Many thanks!
The block design or Altera's Platform Designer are very impressive tools to design. However, knowing that a microblaze/nios connects to an interrupt controller for example is what I still don't understand. Do you need to take a course/learn about computer architecture to understand all those blocks or do the vendors provide them. I feel like if you told me to design LED toggling, I wouldn't know which blocks to connect or how to connect them even though I know where to click on the software to access them. How would I go about that?
Hi stacy, would you be inclined to do private lessons via zoom call?
Hi David, I'm not taking on any more clients at the moment, but will be making more videos in my spare time. You're welcome to suggest a video idea if there's anything specific you're interested in.
@@FPGAsforBeginners I struggle with vivado.. petalux.. the mpsoc platform has alluded me. I have a good grasp on fundamentals, system Verilog, verilog, hdl, that I can do fine, hard logic coding also isnt a struggle. Its Xilinx's software stack that's always humbling me. I find myself in Quartus alot, just to avoid feeling bloated and inefficient with vivado.
Could you do a fresh onboarding video?
perhaps targeting an mpsoc platform, perhaps a zcu102.. A hands on with Xilinx primitives would be cool, DSP preferably.
Thanks for being awesome 💖