Q. 7.15: Using 64 * 8 ROM chips with an enable input, construct a 512 * 8 ROM with eight chips and a

[@Mahmoud-pf1ss]

great explanation thank you so much

[@poojats1261]

i have one doubt , if this circuit is implimented in real world , decoder as some delay so adress maching with that particular data will be missed , so what we can do to not loose or mismatch data between those address
can we use wait state for the decoder , where it generate wait delays?

[@sarithashetty8581]

Assume that a processor has 24-bit address bus and 8-bit data bus. Design a
computer system that interfaces this processor with RAM of size 512 KB made
of 64 KB chips and 64 KB of single chip ROM with address map starting at
locations 400000 and 000000 respectively. Draw a neat sketch of the schematic
diagram showing the interconnections and the address decoder. how design this?

[@sazzadhosen5868]

8M×32 memory module using 512k × 8 memory chips?

[@ajayaj5317]

can you tell me the book name

[@DrDhimanKakati]

Digital design by morris mano and Michael cilleti

[@subhashbathoju2676]

❤️👍

[@letsstudywithbhumika4490]

Hello

[@nadeatarek7329]

شكررا برازر

[@ahmedmohey6645]

العفو برازر فهمك هو كدا

[@kshitizahuja7716]

It is too difficult to understand 😭

[@siddeshs7893]

lightskin stare

[@kshitizahuja7716]

@@siddeshs7893 means??

[@chess_material]

Same for me...but try to understand ❤😊😊