Q. 7.7: A 16K * 4 memory uses coincident decoding by splitting the internal decoder into X‐selection

Q. 7.7: A 16K * 4 memory uses coincident decoding by splitting the internal decoder into X‐selection and Y‐selection.
(a) What is the size of each decoder, and how many AND gates are required for decoding the address?
(b) Determine the X and Y selection lines that are enabled when the input address is the binary equivalent of 8,000.
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Why we take 256 and gates ?

[@lexistencelessence1848]

I think the correct answer is 256+128*128 AND gates.