Hello! I just wanted to thank you for posting these series, I had to do a similar design for a final project of a class and I had no idea where to even begin. This was such a big help! I could not have done it without you! Thank you so much
thank you Hafeez KT for such an enlightening tutorial. Most of this was new for me as i just started with an introductory course in vlsi design in my btech, so i had little knowledge of analog Integrated circuit design. i took up a project on opamps and your videos have helped me throughout with it.
Namaste Hafeez! Thank you very much for these tutorials. A good synthesis of MOS concepts applied to basic opamp design. I learned a lot especially the systematic approach to opamp design.
Thank you for your great playlist, but you have forgotten the design of buffer stage for opamp as you mentioned in your videos, please complete that stage as soon as you can. Also you can try other structures of opamp too, because your explains are well.
Wow they were AMAZING i learned a Lot from it but apparently i can't do them with my cadance version the transistors are not the same but also i can change the specifications of them to match ... any way they were so cool and that shows the very kind of u very appreciated sir looking forward to the next videos . This is 2018😎😚
Hello Hafeez...this series of your lectures is really awesome, will surely benefit many...keep posting such videos...thanks :) One question - you told about finding DC power dissipation using Cadence, is there any similar way to find the ac power dissipation, does ac power really matter?
Hi Hafeez, Your videos are really useful. Thanks a lot. I have a small query. I am going to design an OP-AMP in N-well process. So, I will use the N-MOS and p-MOs exactly opposite in the design you have explained. Will all the formulas you have explained will apply in my design? Is there any specific change in your design flow in my case ? thanks in advance :)
Hello hafeez sir I am using UMC 180nm tehnology I could not able to change length 1um so also not getting proper results. When i give VDC=0.9v at both only then gain is coming otherwise gain is going in to negative value. Why is this happening please clarify my doubt sir. how we need to give differential inputs to get proper gain ?
Hello, I am designing the similar opamp for Ibias 10uA and Cc 8pF. Gain is 93.64db, Phase margin is 60 degrees with unity gain bandwidth of 2.53Mhz. But when the simulate it the transistor M5 and M7 are in triode region. The gain through bode plot is only 44.3db and unity gain bandwidth is only 572kHz. Could you please me on what i need to change to get the transistors M5 and M5 to saturation region.
Hello Hafeez; Gooooooooooooooood very very Gooooooooooooood! I have two Q: 1- with low frequency lets say 1-10Hz, this amp. works fine! 2-if we cascaded this 2 stage with similar 2 stage, is there any effect or we going to have more gain. (60db*60db=1000*1000=1000000 !!!) Thanks Abdullah
Hello Mr Hafeez I am a student at Ho Chi MInh University of Technology in Viet Nam. I have watched your video on 2 state op amp design. I have try it and it works quite well. But when it come to resistive load(200ohm) the gain drop a lot .I am trying to make a buffer state using N mos transistor but the problem is that Vbias for the current mirror and the output of the gain state put the buffer state into triode region. Is there anyway to fix this without changeing the previous design specification of the differential and gain state? Thank you Best Regard Tuong,
Hello Hafeez , Ur lectures are good I required small clarification regarding Drain current equation. Is Still square law equation Valid for Deep Sub-micron CMOS Technology i.e 180nm / 90nm. Thanks in advance
square law is not valid for sub micron technology. But in analog designs we generally use channel length two or more times higher than minimum channel length (L> 2 Lmin). So for hand calculations we can use square law. We will get approximate design using those equations. But we have to tune the design in simulator.
Hafeez KT For >2Lmin channel length also channel length modulation effect and mobility reduction with gate voltage (betaeff is not constant) will come into picture. So there will be large variation in the specifications and simulated values. Can u give any suggestion how to solve these problem? And How to calculate lambda of short channel mosfet, like minimum length if 90nm /65nm technology. thank you
Hello! I just wanted to thank you for posting these series, I had to do a similar design for a final project of a class and I had no idea where to even begin. This was such a big help! I could not have done it without you! Thank you so much
Thank You Hafeez sir for this amazing series of Op amp. Truly appreciate your work.
thank you Hafeez KT for such an enlightening tutorial. Most of this was new for me as i just started with an introductory course in vlsi design in my btech, so i had little knowledge of analog Integrated circuit design. i took up a project on opamps and your videos have helped me throughout with it.
Namaste Hafeez! Thank you very much for these tutorials. A good synthesis of MOS concepts applied to basic opamp design. I learned a lot especially the systematic approach to opamp design.
Thank you Sir. Your videos are very helpful and you explanation is good sir.
I enjoyed and learned so much with your tutorials. Thank you!!!
sir please keep making such videos !
Thank you so much. Your videos were very useful. Nicely explained.
Hi! thanks for the videos, they are very helpful! Could you put the CMRR and the PSRR analyses for this OP AMP?
Thank you for your great playlist, but you have forgotten the design of buffer stage for opamp as you mentioned in your videos, please complete that stage as soon as you can. Also you can try other structures of opamp too, because your explains are well.
in general we are not allowed to change channel length n? so for increasing ro there should be some alternate approach ?
Wow they were AMAZING i learned a Lot from it but apparently i can't do them with my cadance version the transistors are not the same but also i can change the specifications of them to match ... any way they were so cool and that shows the very kind of u very appreciated sir looking forward to the next videos . This is 2018😎😚
Sir can you please do some series on oscillators. Your videos are helping me a lot. Thankyou so much sir
Really good job Hafeez.
Thank you very much.
May I ask you to add some videos to show how to design a folded cascode amp in cadence?
thank you SIR good jobs try to keep more videos
Hello Hafeez...this series of your lectures is really awesome, will surely benefit many...keep posting such videos...thanks :)
One question - you told about finding DC power dissipation using Cadence, is there any similar way to find the ac power dissipation, does ac power really matter?
u mean small signal power dissipation? it is not significant
Hafeez KT many thanks!
Please make a video on Fully diff op amp also.
Thanks you very much...........wish u a happy new year sir
You're the best. And thank you.
Thank you for this video. You help me a lot!
Hi sir, will u plz do a video on 'worst case corner analysis', else plz refer me whr i can get document of procedure to do it.
man, thanks a lot!! these videos was very helpful !
I understood everything, keep up the great job! o/
Can I plot the gain using DC analysis? I can get the AC gain using the method you showed but can i get the DC gain with a different method. Thanks
Hafeez KT please upload a video regarding the noise analysis of this opamp design
Will you please tell us how to calculate slewrate,CMRR and PSRR also in cadence
....
Thank You Sir....Great Work....
Thank you so much sir❤❤❤❤❤❤❤❤❤❤
A great playlist.
Hi Hafeez, Your videos are really useful. Thanks a lot. I have a small query. I am going to design an OP-AMP in N-well process. So, I will use the N-MOS and p-MOs exactly opposite in the design you have explained. Will all the formulas you have explained will apply in my design? Is there any specific change in your design flow in my case ?
thanks in advance :)
Hello hafeez sir
I am using UMC 180nm tehnology
I could not able to change length 1um so also not getting proper results.
When i give VDC=0.9v at both only then gain is coming
otherwise gain is going in to negative value.
Why is this happening please clarify my doubt sir.
how we need to give differential inputs to get proper gain ?
What is transconductance amplifier
Hello, I am designing the similar opamp for Ibias 10uA and Cc 8pF. Gain is 93.64db, Phase margin is 60 degrees with unity gain bandwidth of 2.53Mhz. But when the simulate it the transistor M5 and M7 are in triode region. The gain through bode plot is only 44.3db and unity gain bandwidth is only 572kHz. Could you please me on what i need to change to get the transistors M5 and M5 to saturation region.
i want to know too
Operational transconductance amplifier???
You are aersome!!!
Hello Hafeez;
Gooooooooooooooood very very Gooooooooooooood!
I have two Q:
1- with low frequency lets say 1-10Hz, this amp. works fine!
2-if we cascaded this 2 stage with similar 2 stage, is there any effect or we going to have more gain. (60db*60db=1000*1000=1000000 !!!)
Thanks
Abdullah
Hello Mr Hafeez
I am a student at Ho Chi MInh University of Technology in Viet Nam. I have watched your video on 2 state op amp design. I have try it and it works quite well. But when it come to resistive load(200ohm) the gain drop a lot .I am trying to make a buffer state using N mos transistor but the problem is that Vbias for the current mirror and the output of the gain state put the buffer state into triode region.
Is there anyway to fix this without changeing the previous design specification of the differential and gain state?
Thank you
Best Regard
Tuong,
Hello Hafeez , Ur lectures are good
I required small clarification regarding Drain current equation. Is Still square law equation Valid for Deep Sub-micron CMOS Technology i.e 180nm / 90nm.
Thanks in advance
square law is not valid for sub micron technology. But in analog designs we generally use channel length two or more times higher than minimum channel length (L> 2 Lmin). So for hand calculations we can use square law. We will get approximate design using those equations. But we have to tune the design in simulator.
Hafeez KT
For >2Lmin channel length also channel length modulation effect and mobility reduction with gate voltage (betaeff is not constant) will come into picture. So there will be large variation in the specifications and simulated values. Can u give any suggestion how to solve these problem?
And How to calculate lambda of short channel mosfet, like minimum length if 90nm /65nm technology.
thank you
could you please share the source file for this.
Sir can i have the symbol of the opamp in cadence
Thanks a lot
you are literally in every analog related content , damnn
@@chetanggokhale I was jobless those days. I used to upskill myself on TH-cam. Used to comment in every videos to overcome anxiety. :)
@@alterguy4327 Awesome dude what are you upto now ,all that work must have paid off
@@alterguy4327 ...
@@chetanggokhale Yes, I got a job later in a EDA company.
Thank u so much..Sir..!
Thank you a lot sir .
Thank you
Can I get your mail, sir ?
sir can i get ur email id . i have some doubt regarding analysis on Synopsys