hey nice explanation. You said, all the transistors will be in saturation. This need not be the case for the input diff pair right? I can have sub threshold region of operation by compromising with the speed.
It's a technology value that depends on the technology you use. You can aproximate it by simulation (he explains it the single stage design) or you have the dates from the vendor of the transistor
@@bozoqturkmni8137 Brother basically the point is we need to get a good Phase Margin roughly around 60Db, so for that is we see our system it's a Two pole One zero system, now the poles must be arranged in such a manner that the unity gain frequency lies in between the two poles, and so for doing that we use the dominant pole concept, now to decrease the first pole location and bring it closer to origin we see that the value of first pole depends on the capacitor Cc and Ro1 of the mos, but Ro1 is fixed so we need to increase Cc, to do that we apply the Miller's theorem and connect a feedback capacitor on stage 2 so that it will decompose into two capacitors with high values and make that change happen...So that we can achieve our desired PHASE MARGIN.
Thank you so much, I have homework in my electronics course, but I don't know how to do it, you are my savior.
hey nice explanation. You said, all the transistors will be in saturation. This need not be the case for the input diff pair right? I can have sub threshold region of operation by compromising with the speed.
For gm1 (13:05), Where does that 2*pi come from?
+Dkmasteris never mind, it's because originally it's in rad/s, so we divide it by 2*pi to get it in Hz.
Thanks! 1rad/s = (1/2pi)Hz
Hi, I am interested in knowing the calculation for the expression (unCox) that you have mentioned in the video as 300. Thanks in advance
It's a technology value that depends on the technology you use. You can aproximate it by simulation (he explains it the single stage design) or you have the dates from the vendor of the transistor
th-cam.com/video/XLK91PfbsCY/w-d-xo.html
could you please explain me how did you got 30MHz as the gain bandwidth??
i am getting upcox as 2.45m due to which w/l ratio is coming out to be less than 1 what should i do pls help
i need 5000 gain which parameters should ı choose ?
Where id he use gain = 1000 requirement in calculations?
In which video, did you talk about how to find mu and Cox value from Simulation? Please tell me.
th-cam.com/video/XLK91PfbsCY/w-d-xo.html
I cant understand why you put W=2.5um in NMOS and PMOS transistors . I would like to know the reason, please
Uncox value ref video link plz
Isn't the Vth value a thermal related number, rather that having something to do with the threshold voltage?
19:00
Thanks
For what I need capacitor Cc ?
@@bozoqturkmni8137 Brother basically the point is we need to get a good Phase Margin roughly around 60Db, so for that is we see our system it's a Two pole One zero system, now the poles must be arranged in such a manner that the unity gain frequency lies in between the two poles, and so for doing that we use the dominant pole concept, now to decrease the first pole location and bring it closer to origin we see that the value of first pole depends on the capacitor Cc and Ro1 of the mos, but Ro1 is fixed so we need to increase Cc, to do that we apply the Miller's theorem and connect a feedback capacitor on stage 2 so that it will decompose into two capacitors with high values and make that change happen...So that we can achieve our desired PHASE MARGIN.
How to make a differentiator using 2 stage opamp??