Altium Designer RF Impedance Matching (e.g. 50Ω, USB, ...)
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- เผยแพร่เมื่อ 20 ธ.ค. 2022
- In this video I will show you how to use Altium Designer to create controlled impedance traces for your specific board stackup. This will enable you to have impedance matched networks on your board.
I will show you how to calculate track widths and gaps for single-ended and differential pairs.
Thank you for posting this video
You're welcome!
Great video, thanks for sharing
Thank you, much appreciated! Glad to hear you liked it !
thank you so much, it was so helpful
thank you, great to hear!
Nice info, well done, thanks :)
You're welcome, thanks for the kind words!
valuable videos
Thank you, appreciate the kind words!
Is there a way to have a more elegant way (narrower traces to be able to acces neighbor pins of the package as well) to enter into the IC package in your example?
Hi Danny, thank you for your comment! I have tried it on my design from the video (but cannot include a screenshot here unfortunately): it is possible to route out the pins next to the differential pair on the MCU with standard 0.2mm traces.
However, if that would not be feasible for some reason (like much smaller pitch), I would suggest to make the last part of the differential pair towards the MCU as small as you need. And this only over the distance that you need to fan out the adjacent pins. This is less ideal of course, but since it will only be over a very small distance this should not influence imedance too much.
Another option: via in pad on the adjacent pins (but for production you should ideally fill these vias in the PCB production process).
Hope this answers your question?
very nice 🙂
Thank you!
If you have a double layer PCB and you want to create the copper plane with a polygon pour, do you need to create an additional rule to ensure that return path under the differential line is solid? Why you cannot select differential pair (classes) in the return path rule?
Hi Sam, ideally I would always try to work with a 4 layer board for this. If you are forced to work with two layers, I would indeed make sure that you double check it with a return path rule. Haven't experience the issue with the differential pair class there, but you could always try to "force" the rule on a dedicated net name.
Good , but at the IC pins we will get error of pin to trace clearance, should we need to make trace thinner at the IC ,source ? Or just proceed with thinner differential tracks of ICs pad size.
Easiest is to make the trace thinner at the IC pins indeed.
regarding the bottom reference. if you have a 4 layer stackup of sig/pow gnd gnd sig/pow.
from what i understand its a reference to the gnd plane which in this case is the top two and then for the bottom two on the other side.
the idea of a reference plane throws me off a little , is that correct ?
hi @narutopowerdex, just to make sure I understand your question, what throws you off exactly? It is indeed so that ideally you reference a signal to a GND plane. This can be done for signals in the top layer with regards to GND on layer 2, and signals on the bottom layer with regards to GND on layer 3. Does that answer your question?
@@sentineo yep so if i have that stackup no matter what, its referencing the 2nd layer regardless
@@Andreasonline3 if you place a solid plane underneath your high-speed signal, this will indeed serve as the reference plane for that signal.
Hello, When should we use a snake-shaped layout for some tracks? Could you please make a tutorial about this technical ?
This is done for length-matching. There is a video coming up in a couple of weeks on that exact topic, stay tuned!
I have one doubt. Suppose if we use 3rd layer as reference of 1st top layer. Second copper layer are open in that area…Then while calculation , two dielectric and middle copper layer Thickenss and 2 dielectric Er should be added? Eg Dielectric er is 4.8 then the total er = 4.8+4.8 And thickness of dielectric is 0.2 and copper layer is 0,35 mm then total thickness. Is 0.2+.035+0.2 ? Am I correct?
Hi @sijo2084, in that case it is best to just treat it as a thicker layer of dielectric in between. It is important therefore to just use the 4.8 as relative permittivity (and not adding it to another 4.8) but with a larger height. In this case, I would go for a height of 0.4 at permittivity of 4.8 and you should be pretty close to what you need. Hope this helps?
@@sentineo thanks .. now it’s clear
I am confused because the Top and Bottom layers are 1/2oz copper and the middle layers are 1oz copper. Usually its the other way around.
Hi, thanks for your comment. It really all depends on the stackup that you are using. The stackup in this video is a standard 4 layer from a PCB supplier. You can have 18um on top/bottom and 35um inside; but you can perfectly well use the reverse with 35um top/bottom and 18um inside. The available buildups of layer stacks are numerous, I just checked with that supplier: there are 28 options just for a 4 layer stackup production on their side.
So, it all depends on what exactly you would need. However, I would suggest to go with the standard pool on your PCB supplier's side to keep the costs low. Unless you need a specific stackup.
How bout the electrical line length or physical length of the trace, doesn't it affect the impedance of 90ohm meaning it can be of any length we don't care?
Don't confuse transmission line impedance with resistance. As shown in the beginning of the video, the transmission line impedance is a complex impedance and must be equal in every place along the line. This is independent of physical length of the trace. Using the tools to calculate width, spacing and return path will ensure that this is indeed the case.
Looking at resistance of a single trace solely, with increasing length, the resistance increases indeed. But that is something completely different than the complex impedance of the transmission line.
@@sentineo complex impedance always consists of resistance and reactance right or the real and imaginary part.
@@whiteking80 suggested reading: electronics.stackexchange.com/questions/293271/characteristic-impedance-vs-resistance
cheers!
@@whiteking80No complex impedance does not always contain resistance and reactance.
An impedance can contain any combination of resistance and reactance. It can contain one or both.
Resistance is just a subset of impedance.
The characteristic impedance is based on the physical dimensions of the cable, traces, it is independent of length.
sorry.what used of document in this video.can you share it? thankyou.
You can find it here: www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwiMtu6N1c_-AhUR_7sIHfGgCI8QFnoECBgQAQ&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fslla414&usg=AOvVaw21rwX3PbgkNlnMHSa346B7
Sir do you have a video on smartphones Bluetooth antenna? Thank you
Not yet, stay tuned ;-)
No matching components (indictors, capacitors, pi-match etc) needed if we do the coplanar waveguide approach?
Hi, depending on your application I'ld say. If you are connecting an antenna to the trace, you would certainly want to hook this up to a network analyzer and foresee some matching component (check out my other video "Designing a PCB with an antenna" for that). For connecting a standard USB connector you can normally leave out any matching components. So it depends on the speed of the signal (high speed USB: check your matching) and power transfer (antenna connected = you want max power transfer: check your matching).
Hope this helps. Cheers!
@@sentineo Thanks for the response.
My question was related to antenna only. Suppose I have a LTE modem where I want to trace a route between ANT pin to SMA connector. If the trace width and length could able to give me 50, why do I need other components?
Hi @@parthasarathimishra7538 please have a look at this video of mine about this topic exactly: th-cam.com/video/YtmQzJX09Lo/w-d-xo.html&t
@@sentineoSpeed of the signal?
Thought that was fixed at close to the speed of light.
Or do you mean slew rate and operating frequency?
Hi @@deang5622, correct, frequency of that signal indeed. On a sidenote: the wave will not travel at the speed of light along a track on a PCB. Typically we consider 15cm per 1ns travelling speed in a standard FR4 substrate.
Which version of Altium are you using? Thanks.
I am not sure, but think this one was made in 23.1.
I am currently on 23.6