Hay can you make next video on getting the pixel matrix in between dvi_in and dvi_out IPs, so that some constant text e.g., Nielfotech, can be overlayed on the video!
hello, I tried your design on my PYNQ-Z2 but it didn't work, I did changed the constraints code to the z2 I found on Github but still nothing showing on my scree, Any idea ?
Hello, I tried to implement your design on my PYNQ-Z1, using Vivado 2022, and the last version of Digilent Vivado Library, but it doesn't show anything in the output, my pc reconized the connection but my SAMSUNG HDMI display monitor dosn't recognize the connection and didn't show the image, do you have any idea which is the issue?,
I use Pynq-Z2 but the HDMI output with noise. I had fixed it by un-comment this line in *.xdc file - "create_clock -period 8.334 -waveform {0.000 4.167} [get_ports hdmi_in_clk_p]" in the video 8:06 , your xdc file as "#create_clock -period 8.334 -waveform {0.000 4.167} [get_ports hdmi_in_clk_p]", you comment it out. I don't know what happened. Why I need add it in my Pynq-Z2 board?
@@aminemouaz5822 hi, I have the same problem and I tried to fix it for a long time now, but still have only a black screen. have you succeeded by any chance?
@Tony Ho! That constraint was written to create a clock with the specified clock period. This is not compulsory until you need greater control over the clock signal to reduce the slack value.
Wow ! Great video. I followed your video and my pipeline design is now working. Thank you very much. Keep it up.
Hi, i generated bitstream file but .ltx file is not generated to update in debug probes. Can u resolve this issue?
Thanks
Can you demonstrate, some image processing on input frame!
Hay can you make next video on getting the pixel matrix in between dvi_in and dvi_out IPs, so that some constant text e.g., Nielfotech, can be overlayed on the video!
Stay tunned! I will make another video for it. Thanks for your support.
hello, I tried your design on my PYNQ-Z2 but it didn't work, I did changed the constraints code to the z2 I found on Github but still nothing showing on my scree, Any idea ?
Let’s use ILA in the pipeline to debug
Hello, I tried to implement your design on my PYNQ-Z1, using Vivado 2022, and the last version of Digilent Vivado Library, but it doesn't show anything in the output, my pc reconized the connection but my SAMSUNG HDMI display monitor dosn't recognize the connection and didn't show the image, do you have any idea which is the issue?,
Hi, you can use ILA to check whether is pipeline is functional or not. This is the best to find out the issue. Especially, check the “locked” status.
Nice video .
could you help me to get the frames from the video an edit them?
I will make a separate video. Stay tuned.
@@nielfotech4684 when you will make a vídeo doing the same but using vdma?
Thanks for your interest. I will be publish similar design in coming weeks that will cover frame processing.
@@nielfotech4684 great. I will waiting for it.
I use Pynq-Z2 but the HDMI output with noise.
I had fixed it by un-comment this line in *.xdc file - "create_clock -period 8.334 -waveform {0.000 4.167} [get_ports hdmi_in_clk_p]"
in the video 8:06 , your xdc file as "#create_clock -period 8.334 -waveform {0.000 4.167} [get_ports hdmi_in_clk_p]", you comment it out.
I don't know what happened. Why I need add it in my Pynq-Z2 board?
hi i followed this tutorial step by step when i finished flashing my pynq Z2 Board i got only black screen can you help me??
@ Tony Ho
@ Nielfotech
@@aminemouaz5822 hi,
I have the same problem and I tried to fix it for a long time now, but still have only a black screen. have you succeeded by any chance?
@Amine Mouaz @edouard lagesse
What kind of issue are you facing? Could you give me some details?
@Tony Ho!
That constraint was written to create a clock with the specified clock period. This is not compulsory until you need greater control over the clock signal to reduce the slack value.
unable to make external pin connections in Vivado 2017.4 for TMDS signal
Try to find another ip (newer ) dvi to rgb
add TMDS interface in the ip repo from digilent vivado github master
@Sandeep Kodam (M21EE060)
Adding TMDS interface, as replied by @Abubrata Roy, will solve your issue.
Hello,Can you help us to implement this in Nexys video Artix-7 FPGA board
Yes
Can we use the same set of IPs for Nexys Video board?What are the changes to be made if so? @@nielfotech4684
Hi programming
Hi, can u please share your mail address? i have few questions. im planning to do a hdmi video pipeline project.