RTL to GDSII | ASIC design flow | Front End Design | part I

[@ShitongJiang]

Thank you for sharing! Well done!

[@anandrajofficial1]

Thanks for watching!

[@mr_penchal]

Thank you so much for sharing your knowledge.
More power to you!

[@anandrajofficial1]

Happy to see this type of comment.it really motivates me for making video.

[@Funbaaz456]

Sir aap screen record kaise krte Hain aur audio bhi
Any app or software ?

[@anandrajofficial1]

Laptop only

[@SabnamParveen-v3j]

Sir, if I am designing a combinational circuit then how to write sdc constraints.

[@anandrajofficial1]

in that case give only input and output delay bcz there will not be any clock

[@rezapapi6544]

Sir, could you please show the code inside dft.tcl?

[@sukanyaverma6565]

Can you provide some open source tools to do this project

[@Arul_R]

Hi

[@PrinceSaini-y7e]

What are the things you skipped in this ?