RTL to GDSII | ASIC design flow | Backend Design | part II

[@saitejakatta664]

Thanks bro❤️, i watched all of your videos

[@anandrajofficial1]

Hope you have understood the flow

[@PrinceSaini-y7e]

Innovus (back end design: PD) for flooring: 3:10
Power Plan: 9:25
Placement Routing: 16:20
CTS: 26:30

[@RAJEEVKUMAR-oi8di]

Bro can you show...
Scan chain insertion code and dft.Tcl

[@rezapapi6544]

Sir, I got this error when I tried to synthesize the clock:
Cannot run 'create_clock_tree_spec' as no delay corners are defined.
do you have any idea why this error appeared?

[@rezapapi6544]

also you include a counter.view file which I dont know who to generate it.

[@anandrajofficial1]

Have you defined all MMMC?

[@anandrajofficial1]

@@rezapapi6544 when you will save after creating MMMC ,it will be in .view file

[@rezapapi6544]

@@anandrajofficial1 I dont know how to create MMC File. Since I only make the syn.tcl, but there was another file tc.tcl which I dont have it

[@anandrajofficial1]

@@rezapapi6544 check any video from yt or Google it. I will make it in future

[@Ayushkumar-hj3wz]

Bro Can you show how to write TCL file

[@anandrajofficial1]

Ok i will do that be connected .

[@Ayushkumar-hj3wz]

I request you to do it soon as I'm from IITD and I've to submit project by 23 May

[@anandrajofficial1]

@@Ayushkumar-hj3wz you want TCL for synthesis or other ?

[@Ayushkumar-hj3wz]

@@anandrajofficial1 for synthesis only

[@anandrajofficial1]

@@Ayushkumar-hj3wz th-cam.com/video/xNkf2tadsDU/w-d-xo.html check this