Thanks for making this ASIC flow introduction video. You can also list physical verification tool. I am not familiar with this stage, are DRC/LVS/ERC using bundled different tools, like Calibre for LVS, DRC using other? not like logic synthesis or PNR, correct me.
Yes dear, Calibre of Mentor graphics is the very popular tool for PV. Other tools are IC Validator (ICV) of Synopsys. Cadence has also tool but very less used for PV.
Good video to understand the RTL to GDS flow. I have one question, I am looking for an advance design standard cell GDS layout for doing electrical simulation. is there any accessible resource? or the only way is doing all this flow?
Wow! Audio quality is greatly improved. Thanks team vlsi
Thanks Vikas.
Wonderfull Thank you for sharing with us this beautiful work
My pleasure 😊
Thank you sir. It was a good brief explanation.
Thanks a lot Udit.
Thanks for your video! It's clear and easily to understand!
I've a little quesion is what's the full name of GDS?
Thanks!!!!
GDS is acronyms of Graphic Data Stream. Which contains geometry of all the layers used in layout design.
Thanks for making this ASIC flow introduction video. You can also list physical verification tool. I am not familiar with this stage, are DRC/LVS/ERC using bundled different tools, like Calibre for LVS, DRC using other? not like logic synthesis or PNR, correct me.
Yes dear,
Calibre of Mentor graphics is the very popular tool for PV. Other tools are IC Validator (ICV) of Synopsys. Cadence has also tool but very less used for PV.
@@TeamVLSI thanks
Sir can u explain all numerical problems in setup , hold,CTS,sta etc
Yes, I will cover some numericals in STA concepts series.
Good video to understand the RTL to GDS flow. I have one question, I am looking for an advance design standard cell GDS layout for doing electrical simulation. is there any accessible resource? or the only way is doing all this flow?
Sorry, I did not get your query. Can you elaborate me what you want?
RTL full form
Hi Mandava,
RTL is short form of Register Transfer Level
@@TeamVLSI thank you