MOSFET Overlap Capacitance Explained

[@rocioparra7124]

Oh my god, I took my first semiconductor physics course the year before this playlist was posted and didn't find any good content on TH-cam explaining it. Now I'm taking a power electronics course and needed some refreshing of the contents, and this is just PERFECT! I wish I had them when I first needed them, I was really desperate lol. THANK YOU!!! These videos are amazing

[@BrutalGames2013]

You are the only one who explained the overlapping capacitance Cov. Thank you, you saved my exam :D

[@JordanEdmundsEECS]

My pleasure! It's one of those subtle but important topics that doesn't come up much, I am glad you found it useful.

[@user-kl6ld6px6s]

crisp and ro the point explanation you are the best last minute guide in exams

[@trumpwastaken6779]

You deserve more views, made everything clearer thank you

[@JordanEdmundsEECS]

Thanks :D I'm glad you found it helpful

[@SumanKumar-rf1xb]

Thanks for the explanation. Have one question. How does this gate-drain capacitance vary with varying drain voltage. Why is Cgd called variable where as Cgs is fixed

[@jieunkim2433]

Thank you for your explanation! From south KOREA :):)

[@rockspoon6528]

*Sips on MOSFET*
Mhm, yes, a good year. Excellent doping concentrations, and a very full body.
Exquisite.

[@manojgutha5686]

Very nice video with good content

[@salomonirutingabo7341]

This was amazing, thank you so much 😊🙏🏾

[@hawk9938]

this video helps me a lot. but still I have some questions for MOSFET cap. Is it changed by operation region?
I think cap will reduced when MOSFET operate at triode region than the cutt off region by the electrons are moving.

[@JordanEdmundsEECS]

Hawk Good question! This capacitance is only formed between the deain/source well regions and the gate, neither of which is really affected by the region of operation, so we treat this capacitance as constant.

[@hawk9938]

@@JordanEdmundsEECS thanks for your good video and comment!

[@manojgutha5686]

@@JordanEdmundsEECS you mean to say , it won't effect delay of cell also???

[@waqasali-ts2kv]

Thats great.. Can you please also explain how can we practically measure sub threshold current in MOSFETs

[@JordanEdmundsEECS]

With a really nice SourceMeter (like a Keithley 2400).

[@DarkLambfromthesun]

Thanks, keep doing videos like this

[@JordanEdmundsEECS]

Will do :)

[@swatisrivastava7385]

If depletion width is xd , then what's about overlap cap , is it Cox.xd.w , is there any relation between xd and Ld ??

[@JordanEdmundsEECS]

Not as far as I’m aware, Ld is a physical width and refers to things about the manufacturing process. Why the “d” and not something more sensible like “o” (for overlap)? I’m not sure.

[@rg1346]

Thank you sir.

[@门楚-c1c]

thank you sir

[@JordanEdmundsEECS]

And thank you for the thank-you :)

[@astrologyfit]

will save my life tomorrow