#1 Ben Eater's 8 Bit Computer (SAP-1) in an FPGA: The Registers
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- เผยแพร่เมื่อ 1 ต.ค. 2024
- This is the first video in a series of videos on implementing Ben Eater's 8 Bit Computer in an FPGA.
Ben Eater's 8 Bit Computer is actually based on a computer called the SAP-1 from the book "Digital Computer Electronics" by Paul Malvino and Jerald Brown.
I wanted to do a series of videos that present a practical introduction to FPGAs and I thought it might be interesting to build Ben Eater’s 8-bit computer in an FPGA. This could be a practical example to learn about FPGAs and how CPUs work at the same time.
In this first video, we will implement a generic register module in a hardware definition language called Verilog. We can use this generic register module to implement all of the registers in the SAP-1 computer including the A and B registers, the Output register, the Memory Address register, and the Instruction register.
Once we have completed implementing the SAP-1/Ben Eater 8-bit computer architecture, we will expand this design with more memory, more CPU instructions, and we will even be creating an assembler for our expanded computer!
I hope this video will be educational and entertaining and maybe you will learn some Verilog and FPGA design along the way via a practical example.
And make sure you subscribe to my channel!
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Hi Phil, thanks for sharing your knowledge.
Is it possible to share one_shot.v, debounce.v and clock_pulser.v?
thanks
Since he shows all 3 short files starting at 12:00 it’s possible to take screenshots and re-create them.
Sweet Jesus! Talk about jumping in at the deep end!!! Slow down and explain things - certainly not beginner friendly
This isn’t for beginners …. Do first year CS undergrads build CPUs from scratch in HDL? I’ll give you a hint. No.
You don't share your files so, although I am happy for you that you can do this, I would rather learn how and be able to follow along or buy a kit or something. As is, this is just a waste of my time watching someone else do what I would like to but cannot because I am not given the source.
Great! Liked and Subbed!
Suddenly I had to think of the theatrical performance of Emily Brontë's "Wuthering Heights" by some English Semaphore Society using sign flags. One of the classical jokes of Monty Python.
Ben Eater went back to an ancient processor and plunged it onto a breadboard, don't forget; modern computers were already invented by then. With wires and old fashioned passive components an environment for the electrical dinosaur could be made. Then one could practice like it is 1975 again. We are not really going back half a century, it is only make believe. For the fun, for the sport. Like there are now still competitions in stenography (shorthand) while there are almost no secretaries left that use a speedy notation while being dictated a letter.
An FPGA is so fast, and so completely overwhelming in capabilities that it is difficult to follow how the emulations of ancient chips were done. It is like shooting an irritating insect with a molecular disintegrator.
I gave you a big thumbs up. I tried to give you more thumbs up but only the odd numbers are counting.
Is there any reason to sort if-else clauses with the most commonly activated first? As a programmer I will instinctively do that if I know that a signal, like reset, will be used much less often than, in this case, latch.
In the FPGA, it makes no difference. The code is not executed sequentially. Rather, it is translated into logic that is executed in parallel. So the real concern for the programmer is to make the code readable. The "reset-first" way (like done here) is very common, although I prefer otherwise.
I love the dub-ah-yah bus. 😊
Hi Phil,
what are the extensions used for Verilog in 'vscode'?
Most excellent video. I have been searching for a series like this for a while now. I have the DE2-115 and would love to follow along this journey. Thanks for sharing.
You mentioned you would make your verilog code available but I do not see any link. Could I please get a copy? I am trying to follow along and have a de2-70 so the code should be easily refactored. Possibly putting the quartus verilog files on a github site?
I built all of Ben Eater’s projects, and I’d love to learn an FPGA that doesn’t use Vivado so I’m going to love this. I even bought a copy of that Malvino book.
Oh it appears you don’t answer questions and/or share the files you said you’d share, unfortunately. However! It appears we can just take screenshots after all.
It looks like you're calling these registers latches. what differentiates a latch from a flip flop?
Using in and out ports does that result in using different resources in the fpga? Tri-state buffers for example. And are these limited in availability
Looking forward to following this. I have a de2-70 and a couple other fpga dev boards and want to get back into hdl programming.
Can you please tell me the verilog extension you are using in vs code? If you also program in vhdl and could suggest a code extension for that it would be appreciated. Thanks
Ohh man this is high on my todo list .. i'm currently designing/implemeing my cpu in software .. fpga is next
Excellent video, excellent explanation, I loved the way you explain how to program in verilog
Most interesting - Thanks for putting it "out there" :)
Would it be possible to release the Quartus project files at GitHub or somewhere so that people can download and study it?
I second that request
I third that request!
Very interesting project
cool
As i know FPGA doesn't support Tri-State wire inside FPGA. So, it's kind of impossible to implement W bus as it shown on schematic. It's interesting how you gonna overcome this difficulty.
There is no difficulty. The design is working in the FPGA so, no problem.
Big muxes
It's true that FPGA's have no intrinsic support for internal tri-state busses. However, the synthesis tool knows that and translates/converts the tri-state signalling into LUTs (probably multiplexers).
That being said, I don't like uses tri-state internally, precisely because there is no intrinsic support.
I guess it's a matter of coding style and personal preference.