I think it depends on your definition of "simple". Fewer parts and a streamlined design? Yup. Easier for me to wrap my poor brain around? Most certainly not. :) But the explanations are excellent. Thank you!
Thanks, yes, that's why it's posed as a question rather than a statement. You might want to look at the Pure Turing th-cam.com/play/PLjQDRjQfW-87Jbng4CllA9G12HLar0iF8.html or Turing6502 th-cam.com/play/PLjQDRjQfW-84j-jLvrbEeDvGl0QrhX9p7.html playlists to get a better idea about how it works. Takes a bit of commitment, but once the penny drops, it's much more straight forward than it appears.
Exactly my impression. Less parts doesn't mean design is any easier to understand and/or use. For circuits which do very specific things this might be good approach than throwing more chips and microcontrollers at the problem.
I'm just learning about digital circuit design. The idea to use an EPROM and a D-latch buffer as a finite state machine, and make that the core of your CPU design is so elegant! I'm continually impressed by all the brilliant people over the years who have contributed to this corpus of design techniques that make all these systems possible.
@@DrMattRegan It was interesting how you introduced the concept of Turing completeness to justify the idea that all you needed to add to your finite state machine was the ability to access sequential memory in order to emulate the SAP-1. I was surprised again to see that you could vastly simplify the circuit by putting all the registers in RAM, except of course the address register. It's so obvious in hindsight, but I would not have thought of it. You also wind up with far fewer control lines. I would have liked to have seen a discussion on how that impacts performance (number of clock cycles for an operation). I didn't read through the comments to see what others said, but I think the two stack FSM should be Turing complete. By popping values off one stack and pushing them on the other you are effectively moving through a sequential memory.
Yes, the two stack FSM is Turing complete. I go over a 1-bit 6502 design in the Pure Turing playlist. The first machine even has a sequential access memory. It takes about 3 million clocks per 6502 instruction. Most of that is skipping out read and write the memory. When you add in random access main memory, it goes down to about 3000 clocks/instruction.
Lots of people are building on Ben Eater's machine but, of what I've seen, this one is adding a lot more LEARNING... which is the whole point of building an SAP in the first place. NICE!
Those commonly available header strips will quickly ruin a solderless breadboard but with a little searching you can find similar headers with slimmer pins that fit into solderless breadboards beautifully. I'm looking forward to the rest of this series.
I suspect they will probably destroy the boards, but i think one off use is OK. Once i've built a board i usually don't disassemble them. I'm sure i'll come up with a new idea for a video the moment i pull it apart.
~18:40 and sporadically from here - That made my day, thanks! 😂 Having watched Ben Eater's series, as well as your Turing6502 series, I have a few observations on some of the points you make near the start of the video: 1. To my mind, this Turing-SAP-1 makes for an excellent _follow-on_ project to Ben Eater's discrete SAP-1. I think the process of translating the discrete SAP-1 to an implementation of state diagrams and rulebook entries for your style of finite state machine would be a lot easier to digest as a home-brew project than say the 6502. (FWIW, I found the videos on the Turing6502 very interesting). 2. Following on, whilst Ben Eater's SAP-1 is very limited, in many ways I believe that one might be a better starting point for folk who have only just started peering past the veil of the CPU package, since there is a physical 1:1 relation to a module on the SAP-1 in discrete components that can then be tied to a block diagram of a basic 8bit processor. - Same for demonstration purposes for showing the basic innards of a CPU to an absolute beginner and the workings thereof. - On the other hand, the Turing-SAP-1 abstracts these functional blocks into its micro-code, but is a good vehicle to demonstrate this FSM implementation of a usefully functional Turing Machine. 3. The build for this "Turing-SAP-1" certainly has less components, but arguably, the largest contributors for ease of the build come with use of the '574 as well as those custom stripboards with pin-headers ... I haven't looked recently, but I wonder if it is still possible to buy stripboard style of veroboard these days :)
Thanks for the feedback, much appreciated. I think Ben Eater's series is very good, and my thinking at the time was more to augment what he'd done rather than replicate it. The place to go after you'd watched all of Ben's videos. That said, i did deliberately spend quite a bit of time explaining the SAP-1 for those that hadn't watched it. The other series that lead on from the SAP-1 are the SAP 6502 and SAP 6502 Microcode series. It takes the SAP-1 design as is and just beefs it up a bit to run 6502 code, i spend quite a bit more time on the microcode than Ben does in the second series. I have an SAP 68000 series on the back burner, where i take the SAP6502 and beef it up to 16-bits and make it run 68K code. BTW: i'm curious to see what you think of the second video in this particular series, it's actually one of my favourite videos on the channel.
@@DrMattRegan Yes, your intent becomes clear as one moves through the video - With that in mind, perhaps the goal of your opening remarks was to invite engagement with the video, which it certainly has! I can see why the second video in this playlist is your favourite: That is a very neat and tidy summation of the FSM, Turing Machines, plus several Comp. Sci. topics related to these and tying them together. It's a great launching-pad into your revised explanation of your architecture for the FSM-based Turing machine and the enhancements in this iteration - Noting that your earlier material explaining the Turing6502 concepts was already very good. 👍 My primary point of interest for this playlist was in fact, episode 3 (which I will be re-watching a couple of times), since the SAP-1 instruction set is very small and therefore well suited to demonstrating the process of deriving the state diagrams to build your Turing-FSM's "rulebook" to a point one can _really_ understand it. - The reason for this is looking at approaches to architect microcode when "rolling your own" CPU --- Side note: As to FSM implementation of the mighty 68000 -> I salute you! TBH, whilst I love the 68k, I'd probably prefer watching your "remastered" Von Neumann Architecture extensions to SAP 6502 series first, if that remastering is not complete yet.
I am trying to learn about how computers work and may build a ttl computer in the process. The think I have had the hardest time understanding from looking at schematics was the BUS lines. The schematic made it look like they are all connected, but I couldn't figure out how it would work if they were... Now it makes sense it's just a standard for drawing those wires without drawing each one individually. Thanks!
@@gordonw9208 yep, the convention is to draw wires thin and busses thick. Sometimes there is a slash with a number to indicate how many wires. The schematics become in readable if all the wires are drawn. You may also want to look at the Turing6502 series after this.
This is very clever! But, it serves a different purpose than Ben Eater's series. Ben shows how each component of a computer can be made from simple binary logic and then shows how each subsystem plays its unique role in the overall computer architecture.
Your VGA by ROM design crossed my radar screen for the first time yesterday. (Video generation has long been near and dear to my heart.) The very next day The Algorithm brings me SAP-1. Nothing to do now but subscribe! I have some GALs and a PAL programmer from back-in-the-day. Was going to make a SAP-type machine out of 16V8s, an SRAM, and an EPROM. The latest idea was to use the GALs in a bit-slice fashion, sort of à la PDP-8.
Welcome. If you are serious about building a machine, you might want to look at the SAP-6502 playlist. It's the same architecture as the SAP-1 but it's been bulked up to run 6502 machine code. The microcode is available through github and i'm concurrently doing a series explaining how the microcode works.
@@DrMattRegan I think your approach to SAP-6502 is absolutely brilliant! The way you leverage giant inexpensive EPROMs, and the way you use C to create their contents, was amazing! As far as throughput goes, do you think your SAP-6502 capable of 1 MIP? Or if not, would it at least be capable of the throughput of an NMOS 6502 clocked at 1 MHz?
This reminds me of old style mechanical devices with motors and various levers. Number of parts was very important and engineers used all tricks to simplify design some times making it quite hard to understand internal logic.
If you've got some time up your sleeve (several hours), i'd recommend watching this playlist th-cam.com/play/PLjQDRjQfW-84j-jLvrbEeDvGl0QrhX9p7.html It goes over the theory in more detail.
You can absolutely program FPGAs by programming the CLBs manually, without any abstractions. You can tell what bits you want inside the CLB and where the CLB should be, and how it connects to other CLBs. The compiler only does the routing in this case, which you can inspect if you really need to (I had to). You may even control the routing too, basically sidestepping the compiler, but that can be difficult depending on which type of FPGA you want to program.
At a guess, what percentage of people who use FPGAs use their own routing? I suspect you may be the exception to the rule, but that doesn't necessarily disprove the rule. I would say the vast majority use an HDL, so there is a layer of abstraction except for the super user. Some people like to re-write the microcode in their x86 machines, they are skipping the abstraction also.
Ha! I didn't think I was "taking it to the extreme", I was just trying to do more complicated math 🙂 I am curious how you will do the math with no ALU. I think I see it with the EPROM, but I will await your next video to learn.
Hi Michael. Great to hear from you, i've been watching you develop PUTEY-1 from the start, it's getting pretty close to the 8-bit CPUs of the era. Hope you don't mind me mentioning it ! Yep, it's all done with the EPROM, next video should be out soon, (i'm sure you know that editing is the longest part of the process).
Yes, you need weak pulldown resistors on the outputs and reset is actually the output enable signal. I'm a recent convert to the 574 but it makes the jumper boards much easier
My guess for the seven bit board is that it's for output and ASCII is a seven bit code. But for testing you wanted to make sure all eight were working. As an aside it's good that the data bus pins in those chips are contiguous and in the same order. I have worked with a few chips where they're not and you wonder why the IC design engineers thought it was a good idea.
Good guess! But it was a much more practical reason. I do want to run 8-bits of the w-bus up to the top of the board. The maximum distance between the busses on that side of the 27C322 was 4 pins. So to keep everything aligned at the top of the board, the busses can only be 4 pins apart. The SRAM on the lower left uses the bottom 4 pins for data and ground, so the w-bus needs to abut the SRAM chip, but when I tried the 8-pin board I couldn’t squeeze it in. Martin, you’ve watched most (if not all) of my videos, I’m trying to approach the same material from different angles, what do you think?
@@DrMattRegan I like how you are showing how this simple machine can emulate other more complex machines. The part count was especially instructive. It does it by moving the complexity into the rulebook which is essentially software. It's sort of the logical conclusion to RISC and shows how all computers have the same capabilities. Although those big EPROMs themselves have a lot of complexity stashed away inside them!
@@mheermance true, there is considerable engineering behind the memories. What I’m hoping to achieve is to basically show the nugget at the core. So when people see really complex architectures they don’t get intimidated and can break it into pieces. I worked in the Architecture group at Nvidia during the Tesla and Fermi period and it was the only way to understand the GPU.
This is a really interesting video, I'm really keen to see where it goes. Have you pushed it to see how fast it will run? Slu4 got his breadboard CPU to push quite a few mhz recently!
I was amazed he could get 8 MHz on a breadboard. I struggle above 1 MHz on breadboard. Even If they run, they are unreliable. The PCB version of Turing6502 runs at 3.58 MHz. I have some 50 ns EPROMs/SRAM, I might crank this board to see how it goes. Below 250k is usually for fine. Some of the PureTuring examples had to run for days error free to get enough data to see Pac-Man move.
@@DrMattRegan it's an amazing series of projects you have done. I really enjoy your explanations of why you have made the choices you have and how they are implemented. If I had to offer minor negative feedback it would be the nightrider gag got a little old for me. But I'm also too young to have seen the series!
@@colonelbarker all feedback is good 👍. It’s funny I was talking to someone else about it tonight and they said keep knight ridder thing to a single video.
@@DrMattRegan that might be the way. It's great method for testing that the state machine is working. I'd love a video explaining the difference in the two state machine models you mentioned. It sounds like an interesting topic!
Well, Gigatron calls itself a TTL machine and it uses a big ROM. Can't think of too many "TTL CPUs" that don't use microcode in a ROM. TTL somewhat means not an FPGA or software core.
What would be interesting would be to build a simulated NES on a breadboard... As for the cartridges or the games (roms)... that's were EEPROMS would come in. Just have an external board that you'd plug your EEPROM into and connect that to the systems input bus. Now as for the display, audio and the controllers that'd be a different story. However, I think that this would be a pretty cool project to complete.
@@DrMattRegan Yeah, I had the same sentiments. The APU could be issues too. However, you could do 3 different bread board builds, one of the CPU, one for the PPU, and one for the APU and have them connected in the same manner as the original NES bus. Then the fourth module would be the I/O interface for the cartridges, controllers, and a/v outputs. It would be a fairly big build. It would also be an interesting build to see a working NES on a breadboard. However, the timings could be an issue due to the limitations of the bread boards and the sizes and lengths of the wires...
Interesting, although I'd like to see it transferred to a PCB, as tying up that many proto boards seems wrong. As for the EPROM state machine, I was thinking of a design using just an eprom, with the clock going into one of the address pins, so the EPROM has two almost the same banks that get alternated between by the clock. There is of course one big downside to this machine, all your code is hard coded into an EPROM, no keypad or serial port to allow code entry, so one is stuck forever erasing chips.
6:00 Same here lol. I loved hacking Roblox. Id go on daycare simulator games and make my own script to spawn in a shit ton of terrorist NPC's and clown cars. There was this spaceship game where I would make whole armies of bots to just mine stuff for me and fight too lol. But then I really started to like coding and got invested into it. Now i bought some parts off Alibaba and im gonna try to make my own SAP-1 build lol. I might look into this cus it sounds cheaper
@@DrMattRegan That sounds sick. Il definitely look into it. One cancerous thing abt breadboarding up a computer though is definitely keeping the wires neat. Im honestly tempted to just use a perfboard and wire up everything with jumpers, and hide the cable monstrosity lmfao. I wish it was possible to use a 3D printer as a plotter and pump out good quality PCB's
I do discuss this in the SAP 6502 microcode series. I also had a series called Turing to Von Neumann where i went over this as well. I've taken that series down because i'm re-doing it. Add the right memory (Part 2) and an FSA becomes a Turing complete.
The real genius of Turing was that he could only use relays, selectors and punched tape ie single element's, in his design of a working computer. Hiding the complexity of state machines in your eproms may not be a good teaching aid.
I guess “real genius” is like “real beauty “ - in the eye of the beholder. I think the real genius of Turing is that his description is largely agnostic to technology. The terms relay, selector and punched tape do not appear in his 1936 paper - but each to their own. He does refer to a paper tape, but this is somewhat idealised in that it is infinitely long and can be erased and written over an infinite number of times. As for hiding details in an eprom, have a look at the Turing6502 playlist starting at video 6 - plenty of detail about every state in the state machine.
A couple of small beefs... "Automata" is the plural of "Automaton". Your project contain one "Finite State Automaton". Please leave out audio like the samples you use for the tick and cross. They are very jarring. Loved the substance of your video, thanks.
Yes you are correct. I think i'll stick to finite state machine (can't afford an editor). Thanks for the feedback. Have you looked at the Turing6502 series?
@@DrMattRegan yes I have, wonderful series, thanks. I try to follow it all in real time but I go crosseyed before the end. Need to play and stop to absorb fully. I have "The Art of Digital Design" by Winkel and Prosser. I'd like to design my own PDP-8, but extend it from 12-bits to 16-bits for fun. They have the synthesis of a PDP-8 as an example in the text. They make use of multiplexers to create the finite state machine, but I like your approach of EEPROM + '374. It'll be a retirement project for me.
The EPROM + 374 makes a great state machine. Normally, each video should be about 1hr, but I compress it for youtube. Don't be afraid to watch them multiple times and ask questions.
I think it depends on your definition of "simple". Fewer parts and a streamlined design? Yup. Easier for me to wrap my poor brain around? Most certainly not. :) But the explanations are excellent. Thank you!
Thanks, yes, that's why it's posed as a question rather than a statement. You might want to look at the Pure Turing th-cam.com/play/PLjQDRjQfW-87Jbng4CllA9G12HLar0iF8.html or Turing6502 th-cam.com/play/PLjQDRjQfW-84j-jLvrbEeDvGl0QrhX9p7.html playlists to get a better idea about how it works.
Takes a bit of commitment, but once the penny drops, it's much more straight forward than it appears.
Exactly my impression. Less parts doesn't mean design is any easier to understand and/or use. For circuits which do very specific things this might be good approach than throwing more chips and microcontrollers at the problem.
I'm just learning about digital circuit design. The idea to use an EPROM and a D-latch buffer as a finite state machine, and make that the core of your CPU design is so elegant! I'm continually impressed by all the brilliant people over the years who have contributed to this corpus of design techniques that make all these systems possible.
Thanks for the feedback, enjoy the series. I actually like part 2 better in this series. I'm keen to hear what you think about part 2
@@DrMattRegan It was interesting how you introduced the concept of Turing completeness to justify the idea that all you needed to add to your finite state machine was the ability to access sequential memory in order to emulate the SAP-1. I was surprised again to see that you could vastly simplify the circuit by putting all the registers in RAM, except of course the address register. It's so obvious in hindsight, but I would not have thought of it. You also wind up with far fewer control lines. I would have liked to have seen a discussion on how that impacts performance (number of clock cycles for an operation).
I didn't read through the comments to see what others said, but I think the two stack FSM should be Turing complete. By popping values off one stack and pushing them on the other you are effectively moving through a sequential memory.
Yes, the two stack FSM is Turing complete.
I go over a 1-bit 6502 design in the Pure Turing playlist.
The first machine even has a sequential access memory.
It takes about 3 million clocks per 6502 instruction.
Most of that is skipping out read and write the memory.
When you add in random access main memory, it goes down to about 3000 clocks/instruction.
Lots of people are building on Ben Eater's machine but, of what I've seen, this one is adding a lot more LEARNING... which is the whole point of building an SAP in the first place. NICE!
Wow, thanks!
Those commonly available header strips will quickly ruin a solderless breadboard but with a little searching you can find similar headers with slimmer pins that fit into solderless breadboards beautifully. I'm looking forward to the rest of this series.
yep - round machined headers, easy to find
I suspect they will probably destroy the boards, but i think one off use is OK.
Once i've built a board i usually don't disassemble them. I'm sure i'll come up with a new idea for
a video the moment i pull it apart.
@@DrMattRegan yeah, especially if it’s a better quality board (not steel contacts)
The other thing was switching from 74HC374 -> 74HC574 which have all the inputs on one side and outputs on the other.
~18:40 and sporadically from here - That made my day, thanks! 😂
Having watched Ben Eater's series, as well as your Turing6502 series, I have a few observations on some of the points you make near the start of the video:
1. To my mind, this Turing-SAP-1 makes for an excellent _follow-on_ project to Ben Eater's discrete SAP-1. I think the process of translating the discrete SAP-1 to an implementation of state diagrams and rulebook entries for your style of finite state machine would be a lot easier to digest as a home-brew project than say the 6502. (FWIW, I found the videos on the Turing6502 very interesting).
2. Following on, whilst Ben Eater's SAP-1 is very limited, in many ways I believe that one might be a better starting point for folk who have only just started peering past the veil of the CPU package, since there is a physical 1:1 relation to a module on the SAP-1 in discrete components that can then be tied to a block diagram of a basic 8bit processor.
- Same for demonstration purposes for showing the basic innards of a CPU to an absolute beginner and the workings thereof.
- On the other hand, the Turing-SAP-1 abstracts these functional blocks into its micro-code, but is a good vehicle to demonstrate this FSM implementation of a usefully functional Turing Machine.
3. The build for this "Turing-SAP-1" certainly has less components, but arguably, the largest contributors for ease of the build come with use of the '574 as well as those custom stripboards with pin-headers ... I haven't looked recently, but I wonder if it is still possible to buy stripboard style of veroboard these days :)
Thanks for the feedback, much appreciated.
I think Ben Eater's series is very good, and my thinking at the time was more to augment what he'd done rather than replicate it. The place to go after you'd watched all of Ben's videos.
That said, i did deliberately spend quite a bit of time explaining the SAP-1 for those that hadn't watched it.
The other series that lead on from the SAP-1 are the SAP 6502 and SAP 6502 Microcode series. It takes the SAP-1 design as is and just beefs it up a bit to run 6502 code, i spend quite a bit more time on the microcode than Ben does in the second series.
I have an SAP 68000 series on the back burner, where i take the SAP6502 and beef it up to 16-bits and make it run 68K code.
BTW: i'm curious to see what you think of the second video in this particular series, it's actually one of my favourite videos on the channel.
@@DrMattRegan Yes, your intent becomes clear as one moves through the video - With that in mind, perhaps the goal of your opening remarks was to invite engagement with the video, which it certainly has!
I can see why the second video in this playlist is your favourite: That is a very neat and tidy summation of the FSM, Turing Machines, plus several Comp. Sci. topics related to these and tying them together. It's a great launching-pad into your revised explanation of your architecture for the FSM-based Turing machine and the enhancements in this iteration - Noting that your earlier material explaining the Turing6502 concepts was already very good. 👍
My primary point of interest for this playlist was in fact, episode 3 (which I will be re-watching a couple of times), since the SAP-1 instruction set is very small and therefore well suited to demonstrating the process of deriving the state diagrams to build your Turing-FSM's "rulebook" to a point one can _really_ understand it.
- The reason for this is looking at approaches to architect microcode when "rolling your own" CPU
---
Side note:
As to FSM implementation of the mighty 68000 -> I salute you! TBH, whilst I love the 68k, I'd probably prefer watching your "remastered" Von Neumann Architecture extensions to SAP 6502 series first, if that remastering is not complete yet.
Thanks this made FSM's actually digestible for my brain space. Very informative!
Turing6502 is legendary
I am trying to learn about how computers work and may build a ttl computer in the process. The think I have had the hardest time understanding from looking at schematics was the BUS lines. The schematic made it look like they are all connected, but I couldn't figure out how it would work if they were... Now it makes sense it's just a standard for drawing those wires without drawing each one individually. Thanks!
@@gordonw9208 yep, the convention is to draw wires thin and busses thick. Sometimes there is a slash with a number to indicate how many wires. The schematics become in readable if all the wires are drawn. You may also want to look at the Turing6502 series after this.
Excellent!
This is very clever! But, it serves a different purpose than Ben Eater's series. Ben shows how each component of a computer can be made from simple binary logic and then shows how each subsystem plays its unique role in the overall computer architecture.
Thanks. I didn't want to just go over the same ground Ben already covered. Next video will be up soon, i'd be interested to see what you think.
Very different, and very interesting
Thank you! Cheers! Two more parts to the series.
Mad dog! Love your work mate; Really love your explanation!
Thanks, glad you’re getting some value from it.
Your VGA by ROM design crossed my radar screen for the first time yesterday. (Video generation has long been near and dear to my heart.) The very next day The Algorithm brings me SAP-1. Nothing to do now but subscribe!
I have some GALs and a PAL programmer from back-in-the-day. Was going to make a SAP-type machine out of 16V8s, an SRAM, and an EPROM. The latest idea was to use the GALs in a bit-slice fashion, sort of à la PDP-8.
Welcome. If you are serious about building a machine, you might want to look at the SAP-6502 playlist. It's the same architecture as the SAP-1 but it's been bulked up to run 6502 machine code. The microcode is available through github and i'm concurrently doing a series explaining how the microcode works.
@@DrMattRegan I think your approach to SAP-6502 is absolutely brilliant! The way you leverage giant inexpensive EPROMs, and the way you use C to create their contents, was amazing! As far as throughput goes, do you think your SAP-6502 capable of 1 MIP? Or if not, would it at least be capable of the throughput of an NMOS 6502 clocked at 1 MHz?
I’ve had the Turing6502 running at 3.579MHz which is about 50% faster than the native 6502. You might want to check out that playlist as well.
@@DrMattRegan Perfect! Many thanks!
Brilliant video thank you
Enjoy! You might like the Turing6502 series too.
What a great idea. It's great as a teaching tool too.
Thanks for the video.
This reminds me of old style mechanical devices with motors and various levers. Number of parts was very important and engineers used all tricks to simplify design some times making it quite hard to understand internal logic.
If you've got some time up your sleeve (several hours), i'd recommend watching this playlist th-cam.com/play/PLjQDRjQfW-84j-jLvrbEeDvGl0QrhX9p7.html
It goes over the theory in more detail.
Very interesting! Also, it may be unnecessary, but I found the repeated "Knightrider" theme amusing every time. ;-)
Cool. The second video in this series (Memory) is one of my favorite videos. Let me know what you think.
I made the same PCB jumpers for exactly the same reason hehehe
As always, I love your videos and the work behind it.
Cool, thanks! Enjoy!
You can absolutely program FPGAs by programming the CLBs manually, without any abstractions.
You can tell what bits you want inside the CLB and where the CLB should be, and how it connects to other CLBs.
The compiler only does the routing in this case, which you can inspect if you really need to (I had to).
You may even control the routing too, basically sidestepping the compiler, but that can be difficult depending on which type of FPGA you want to program.
At a guess, what percentage of people who use FPGAs use their own routing? I suspect you may be the exception to the rule, but that doesn't necessarily disprove the rule.
I would say the vast majority use an HDL, so there is a layer of abstraction except for the super user.
Some people like to re-write the microcode in their x86 machines, they are skipping the abstraction also.
Instead of messing around with breadboards and unreliable connections, I build the SBC in Proteus. Works flawless in the simulator in real time.
Yes, each to their own. I like seeing hardware coming to life myself.
Ha! I didn't think I was "taking it to the extreme", I was just trying to do more complicated math 🙂
I am curious how you will do the math with no ALU. I think I see it with the EPROM, but I will await your next video to learn.
Hi Michael. Great to hear from you, i've been watching you develop PUTEY-1 from the start, it's getting pretty close to the 8-bit CPUs of the era. Hope you don't mind me mentioning it !
Yep, it's all done with the EPROM, next video should be out soon, (i'm sure you know that editing is the longest part of the process).
@@DrMattRegan Oh, I didn't mind, I was just surprised to here my PUTEY-1 referenced. I'll look forward to your next video.
@@MichaelKamprath new video is up. Let me know what you think when you get a chance to see it.
Which 74HC574 have you found that has a reset? I would have loved that but I had to settle for '273 instead
Yes, you need weak pulldown resistors on the outputs and reset is actually the output enable signal. I'm a recent convert to the 574 but it makes the jumper boards much easier
Cool idea with the BUS pcbs
Thanks, it really made the build much easier
My guess for the seven bit board is that it's for output and ASCII is a seven bit code. But for testing you wanted to make sure all eight were working. As an aside it's good that the data bus pins in those chips are contiguous and in the same order. I have worked with a few chips where they're not and you wonder why the IC design engineers thought it was a good idea.
Good guess! But it was a much more practical reason. I do want to run 8-bits of the w-bus up to the top of the board.
The maximum distance between the busses on that side of the 27C322 was 4 pins. So to keep everything aligned at the top of the board, the busses can only be 4 pins apart. The SRAM on the lower left uses the bottom 4 pins for data and ground, so the w-bus needs to abut the SRAM chip, but when I tried the 8-pin board I couldn’t squeeze it in.
Martin, you’ve watched most (if not all) of my videos, I’m trying to approach the same material from different angles, what do you think?
@@DrMattRegan I like how you are showing how this simple machine can emulate other more complex machines. The part count was especially instructive. It does it by moving the complexity into the rulebook which is essentially software. It's sort of the logical conclusion to RISC and shows how all computers have the same capabilities. Although those big EPROMs themselves have a lot of complexity stashed away inside them!
@@mheermance true, there is considerable engineering behind the memories. What I’m hoping to achieve is to basically show the nugget at the core. So when people see really complex architectures they don’t get intimidated and can break it into pieces. I worked in the Architecture group at Nvidia during the Tesla and Fermi period and it was the only way to understand the GPU.
Whats the name of the software your using for the schematic
KiCAD for schematics, and powerpoint for block diagrams.
This is a really interesting video, I'm really keen to see where it goes. Have you pushed it to see how fast it will run? Slu4 got his breadboard CPU to push quite a few mhz recently!
I was amazed he could get 8 MHz on a breadboard. I struggle above 1 MHz on breadboard. Even If they run, they are unreliable. The PCB version of Turing6502 runs at 3.58 MHz. I have some 50 ns EPROMs/SRAM, I might crank this board to see how it goes. Below 250k is usually for fine. Some of the PureTuring examples had to run for days error free to get enough data to see Pac-Man move.
@@DrMattRegan it's an amazing series of projects you have done. I really enjoy your explanations of why you have made the choices you have and how they are implemented.
If I had to offer minor negative feedback it would be the nightrider gag got a little old for me. But I'm also too young to have seen the series!
@@colonelbarker all feedback is good 👍. It’s funny I was talking to someone else about it tonight and they said keep knight ridder thing to a single video.
@@DrMattRegan that might be the way. It's great method for testing that the state machine is working.
I'd love a video explaining the difference in the two state machine models you mentioned. It sounds like an interesting topic!
Good idea
Calculating Fibonacchi sequence?
Huh??
@@DrMattRegan Interesting work! But wich numbers on display?
@@TheOvvl Fibonacci sequence which is the sum of the last two numbers displayed.
If they contain ducks, then are the really pidgeon holes?
Well, yes. But what about metaphorical ducks in metaphorical pidgeon holes?
using EEPROM truth tables still TTL ?
Well, Gigatron calls itself a TTL machine and it uses a big ROM. Can't think of too many "TTL CPUs" that don't use microcode in a ROM. TTL somewhat means not an FPGA or software core.
What would be interesting would be to build a simulated NES on a breadboard... As for the cartridges or the games (roms)... that's were EEPROMS would come in. Just have an external board that you'd plug your EEPROM into and connect that to the systems input bus. Now as for the display, audio and the controllers that'd be a different story. However, I think that this would be a pretty cool project to complete.
I think the CPU side would be straightforward, its the PPU that would be the killer.
@@DrMattRegan Yeah, I had the same sentiments. The APU could be issues too. However, you could do 3 different bread board builds, one of the CPU, one for the PPU, and one for the APU and have them connected in the same manner as the original NES bus. Then the fourth module would be the I/O interface for the cartridges, controllers, and a/v outputs.
It would be a fairly big build. It would also be an interesting build to see a working NES on a breadboard. However, the timings could be an issue due to the limitations of the bread boards and the sizes and lengths of the wires...
Interesting, although I'd like to see it transferred to a PCB, as tying up that many proto boards seems wrong.
As for the EPROM state machine, I was thinking of a design using just an eprom, with the clock going into one of the address pins, so the EPROM has two almost the same banks that get alternated between by the clock.
There is of course one big downside to this machine, all your code is hard coded into an EPROM, no keypad or serial port to allow code entry, so one is stuck forever erasing chips.
You might want to watch the last 5 mins of the third video!
6:00
Same here lol.
I loved hacking Roblox. Id go on daycare simulator games and make my own script to spawn in a shit ton of terrorist NPC's and clown cars.
There was this spaceship game where I would make whole armies of bots to just mine stuff for me and fight too lol.
But then I really started to like coding and got invested into it.
Now i bought some parts off Alibaba and im gonna try to make my own SAP-1 build lol.
I might look into this cus it sounds cheaper
Good luck with the build. I'm working towards a kit soon.
@@DrMattRegan That sounds sick. Il definitely look into it.
One cancerous thing abt breadboarding up a computer though is definitely keeping the wires neat.
Im honestly tempted to just use a perfboard and wire up everything with jumpers, and hide the cable monstrosity lmfao.
I wish it was possible to use a 3D printer as a plotter and pump out good quality PCB's
I'm confused. Why are there ducks in your pigeon holes?
It was too hard to paint the pigeons!
@@DrMattRegan 😂
Interesting, but not a general-purpose CPU. As you say, it's a finite state machine.
I do discuss this in the SAP 6502 microcode series. I also had a series called Turing to Von Neumann where i went over this as well. I've taken that series down because i'm re-doing it.
Add the right memory (Part 2) and an FSA becomes a Turing complete.
The real genius of Turing was that he could only use relays, selectors and punched tape ie single element's, in his design of a working computer. Hiding the complexity of state machines in your eproms may not be a good teaching aid.
I guess “real genius” is like “real beauty “ - in the eye of the beholder. I think the real genius of Turing is that his description is largely agnostic to technology. The terms relay, selector and punched tape do not appear in his 1936 paper - but each to their own. He does refer to a paper tape, but this is somewhat idealised in that it is infinitely long and can be erased and written over an infinite number of times.
As for hiding details in an eprom, have a look at the Turing6502 playlist starting at video 6 - plenty of detail about every state in the state machine.
A couple of small beefs... "Automata" is the plural of "Automaton". Your project contain one "Finite State Automaton". Please leave out audio like the samples you use for the tick and cross. They are very jarring. Loved the substance of your video, thanks.
Yes you are correct. I think i'll stick to finite state machine (can't afford an editor). Thanks for the feedback. Have you looked at the Turing6502 series?
@@DrMattRegan yes I have, wonderful series, thanks. I try to follow it all in real time but I go crosseyed before the end. Need to play and stop to absorb fully. I have "The Art of Digital Design" by Winkel and Prosser. I'd like to design my own PDP-8, but extend it from 12-bits to 16-bits for fun. They have the synthesis of a PDP-8 as an example in the text. They make use of multiplexers to create the finite state machine, but I like your approach of EEPROM + '374. It'll be a retirement project for me.
The EPROM + 374 makes a great state machine. Normally, each video should be about 1hr, but I compress it for youtube. Don't be afraid to watch them multiple times and ask questions.
Whelp