VHDL Lecture 12 Lab4 - Process in VHDL in Explanation

แชร์
ฝัง
  • เผยแพร่เมื่อ 8 ม.ค. 2025

ความคิดเห็น • 10

  • @bryanchambers1964
    @bryanchambers1964 6 ปีที่แล้ว

    Really appreciate the slow and simple way you explain. Most comp sci teachers assume everyone is a computer genius and do the hardest stuff after two weeks.

  • @ryanwwest
    @ryanwwest 7 ปีที่แล้ว +1

    These are great, high-quality lectures! Thanks for your time!

  • @bryanchambers1964
    @bryanchambers1964 6 ปีที่แล้ว +3

    First vid in series 114000 views, now only 7000. These subjects really weave out all but the most determined or talented (which I have none of).

  • @MaGra1959
    @MaGra1959 7 ปีที่แล้ว +1

    Great VHDL training - but this lectures has a very low resolution (max. 360) and is sometimes hard to read.
    Can you upload in 720p ?

    • @EDUVANCE
      @EDUVANCE  7 ปีที่แล้ว +2

      Sorry for the inconvenience. We will try to upload the upcoming videos in better resolution

    • @manikanthnaidu3969
      @manikanthnaidu3969 7 ปีที่แล้ว

      CAN U PLZ SHARE THE SLIDES?

  • @tchanabachir8254
    @tchanabachir8254 6 ปีที่แล้ว +1

    thanks a lot

  • @fernandoluis53
    @fernandoluis53 7 ปีที่แล้ว

    Great video but please use good quality video and speed up your videos

  • @siriakkiraju
    @siriakkiraju 7 ปีที่แล้ว

    I am using ISE 14.3 I have written the same code but my RTL and Tech Schematics are not same as those shown in this tutorial.The generated schematics are not wrong too as per the code.Why does that happen?

    • @EDUVANCE
      @EDUVANCE  7 ปีที่แล้ว +1

      The RTL and Technology schematic view generated after synthesis of description written in HDL looks similar if we click on both of them. However, if you need to see the difference between the two, you need to double-click on the block to see what hardware lies inside. This procedure is regardless of the version you are using.