Hi, One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock So if it is settle in first clock the latency is 2 else the latency will be 3 How to update design to make this latency a fix value Considering both clock same frequency with phase difference
That is a good question and it is part of a deeper subject, which is CDC. But basically, we can have no timing constraint between the two clock domains. They are asynchronous, which is why we need the synchronizer in the first place. In other words, we have to design our logic to be completely robust to this possibility of the latency being different numbers of clock cycles. You need to ensure that the logic on the capturing side has a long time to capture the signal (much longer than the worst case synchronizer delay) and that it can't accidentally capture a metastable state.
Hi,
One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock
So if it is settle in first clock the latency is 2 else the latency will be 3
How to update design to make this latency a fix value
Considering both clock same frequency with phase difference
That is a good question and it is part of a deeper subject, which is CDC.
But basically, we can have no timing constraint between the two clock domains. They are asynchronous, which is why we need the synchronizer in the first place. In other words, we have to design our logic to be completely robust to this possibility of the latency being different numbers of clock cycles. You need to ensure that the logic on the capturing side has a long time to capture the signal (much longer than the worst case synchronizer delay) and that it can't accidentally capture a metastable state.
@@AdiTemanthank you for your reply
Thanks a lot professor!
You are welcome!