Hi Zach. I am having the exact same issue that the question that your original question had. All my nets show as 200+ ohms, which is physically impossible. But...after reading through the comments, it looks like someone has the answer to what is causing this problem. Which, IMO, if it's correct, is a real problem with the tool. I do have my reference planes setup as polygons. As I bet %95 of people do. So, I'll change them to plane layers and see what happens. As this issue was recognized over a year ago, I am very disappointed that this has not been fixed by now. Would you be able to point this issue out to the appropriate people in Altium and get this in the queue to being fixed? Or, is this something we have to live with...which would be a real problem as sometimes I have to void through layers to polygons on lower layers, that can not be planes, and this, if not fixed, will just not allow me to get correct results. Thanks for all the hard work you put into making these videos. They definitely are very useful. After setting up a design using planes, the values were better...but I think it's still not working right. I setup a polygon pour around both SE and DE nets, and went from 1 mil spacing from signal to polygon, out to 10 and then to 40. No change in impedance calculated by the SI tool at all. Which is clearly not correct. So, the SI tool doesn't appear to recognize polygon pours. That's a real problem if trying to use it to figure out how spacing to a polygon effects impedance in a design.
I have brought this up in the past but I do not know where (or if) this is on the development roadmap. The SI tool has not gotten a lot of love over the past several years and instead there has been a focus on integrations with Simbeor, Ansys, etc. I think this is a case of "squeaky wheel gets the grease"
The answer to the actual question about getting 250 Ohms impedance: Signal Integrity tool uses ground reference only if it is setup as a plane. If you use signal layers with ground polygons-it seems not recognized as a reference ground
As I mentioned in Jim Jewett's question, without looking at the user's specific design it's hard to say what exactly they did to get their result, but in the example board I show the interior layers were defined as plane layers, as can be seen at 6:11. I will say that I have seen someone get a very large result because they had a portion of their trace routed over an area where there was no ground, so of course the solver produces a very large value for the impedance.
I think when it comes to SI Orcad does it much better with it's "impedance vision", where it overlays a color-coded map of impedance directly on top of a PCB such that it's immediately obvious where impedance discontinuities are. Altium needs to implement a similar feature because it's super useful. Also same can be said about crosstalk - Orcad has similar overlay for that as well.
You're preaching to the choir, I've been complaining about that for awhile. They already have the architecture in the backend to do it so they might as well add the feature.
If you're referring to the impedance value you want to design to, this is specified in the standards for the high-speed interface on your component. For example, USB requires 90 Ohms differential impedance, which can be created using 2 traces each with 50 Ohms single-ended impedance. This example with USB is something I have discussed in other videos on routing USB in 2-layer PCBs.
Going back to Zafer Acun's original question ... I'm used to reading about 50-100 Ohms for PCB traces, and the ways to change it being things like trace width, distance to ground, maybe a different di-electric or thickness. These all seem like things the stackup manager would know about, and consider when targetting the intended 100 Ohms. I would expect some variation around vias and such, but getting to 250? Does that indicate a bug? Or at least a serious gap somewhere in the return path, or something else that should be flagged as a design error?
It's hard to say without looking at their design specifically. However I will say that I have seen this happen to me, and it occured because my layout did not match the line design I had calculated in the layer stack. The time I saw this was in a 4-layer RF board that had a portion of the layer stack cleared for a printed waveguide. The feedline was basically being routed over ground on the bottom layer because everything on the inner 2 layers was cleared. The line was sized to have ground 50 Ohms with ground on L2, not with ground on L4, so of course the impedance was through the roof and it was something like 230 Ohms.
@@Zachariah-Peterson That sounds like the sort of edge-case bug I could imagine writing, and it is good that the impedance checker calculates a different way as a cross-check.
@@jimjjewett There is already a simple solution for it though. If you have an impedance profile that has a the reference set to a specific layer (such as L2), then you can apply that profile in the Return Path rule. It should then check if you deviate from that reference layer and it would flag an error.
I had been (perhaps wrongly?) assuming that impedance and Er were similar, and that in addition to reducing the _amount_ of current that flows through, higher impedance (or Er values) would also reduce the _speed_ of propagation. Therefore, the path's average impedance should be weighted not by length, but by time-spent-in-this-section, which would be something like length * impedance, and would therefore mean that sections with higher impedance change the average more than sections with lower impedance. Are my model/assumptions just wrong? Or is that what Altium actually does, but it was too complex to explain in this video? Or is it just that this effect is typically small enough to ignore?
Higher Er means larger refractive index, which means lower speed of light (signal speed). In my opinion they should not do any weighted average, but instead they should show the characteristic impedance and input impedance along each section of the route as a heatmap. Sigrity does it and SIWave does it, so Altium should do it. They have all of the computational power built into the tool already, so it should not be any issue to display that result directly in the PCB editor other than maybe adding a new Panel. If you are going to show a single value as a weighted average, then you could certainly use the time delay in each section as the weight but I don't know that it communicates the impedance information in a new way that is intuitive, maybe I'm wrong though and would have to think about it. If the Er value is the same in all dielectrics in the layer stack then the two weighted averages are equal because the speeds should be equal in all layers except surface layers.
@@Zachariah-Peterson When a standard specifies 50 Ohm, does the "50" actually matter except at the connections? I'm inclined to think in software terms, so that the within-my-own-component impedance (and average impedance, and even variations in impedance) are irrelevant -- so long as the frequency-specific Voltage, Current, and Impedance are somehow correct at the endpoints, but ... I might be missing even something trivial.
@@Zachariah-Peterson Is this implicitly saying that (1) if you have anything beyond 4 layers, impedance controlled traces should get to a via immediately, and spend their time on inner layers (2) if you have 4 layers or less, then in practice, your constraints probably aren't tight enough to worry about this level of detail?
@@jimjjewett The 50 Ohms matters at the connection in terms of the input impedance. That's why impedance transformers and stubs work so well at specific frequencies with narrow bandwidth. But remember the input impedance is related to the line impedance, so it's not just a case that we can say the input impedance plays no role.
@@jimjjewett Getting to the via immediately from the chip output is not an expectation unless you are working at very high frequencies. The layer count doesn't matter so much at that point, what matters is the frequency compared to the distance spanned by the via, that via could be through-hole or blind/buried. For example, it's common to see RF signal launches that pass directly to L3 (through blind/buried via) from a connector or ball out on a component, and they work well up to 90 GHz. If you have only 4 layers or less you could still have very tight constraints, again because of frequency.
![ออร่า (AURA) - JUEPAK feat. SARAN [OFFICIAL MV] | เอแคลร์ จือปาก](http://i.ytimg.com/vi/RY9j7Lzp-FI/mqdefault.jpg)
Hi Zach. I am having the exact same issue that the question that your original question had. All my nets show as 200+ ohms, which is physically impossible. But...after reading through the comments, it looks like someone has the answer to what is causing this problem. Which, IMO, if it's correct, is a real problem with the tool. I do have my reference planes setup as polygons. As I bet %95 of people do. So, I'll change them to plane layers and see what happens. As this issue was recognized over a year ago, I am very disappointed that this has not been fixed by now. Would you be able to point this issue out to the appropriate people in Altium and get this in the queue to being fixed? Or, is this something we have to live with...which would be a real problem as sometimes I have to void through layers to polygons on lower layers, that can not be planes, and this, if not fixed, will just not allow me to get correct results. Thanks for all the hard work you put into making these videos. They definitely are very useful. After setting up a design using planes, the values were better...but I think it's still not working right. I setup a polygon pour around both SE and DE nets, and went from 1 mil spacing from signal to polygon, out to 10 and then to 40. No change in impedance calculated by the SI tool at all. Which is clearly not correct. So, the SI tool doesn't appear to recognize polygon pours. That's a real problem if trying to use it to figure out how spacing to a polygon effects impedance in a design.
I have brought this up in the past but I do not know where (or if) this is on the development roadmap. The SI tool has not gotten a lot of love over the past several years and instead there has been a focus on integrations with Simbeor, Ansys, etc. I think this is a case of "squeaky wheel gets the grease"
The answer to the actual question about getting 250 Ohms impedance: Signal Integrity tool uses ground reference only if it is setup as a plane. If you use signal layers with ground polygons-it seems not recognized as a reference ground
As I mentioned in Jim Jewett's question, without looking at the user's specific design it's hard to say what exactly they did to get their result, but in the example board I show the interior layers were defined as plane layers, as can be seen at 6:11. I will say that I have seen someone get a very large result because they had a portion of their trace routed over an area where there was no ground, so of course the solver produces a very large value for the impedance.
I think when it comes to SI Orcad does it much better with it's "impedance vision", where it overlays a color-coded map of impedance directly on top of a PCB such that it's immediately obvious where impedance discontinuities are. Altium needs to implement a similar feature because it's super useful. Also same can be said about crosstalk - Orcad has similar overlay for that as well.
You're preaching to the choir, I've been complaining about that for awhile. They already have the architecture in the backend to do it so they might as well add the feature.
Thanks a lot. ❤. So, how can we choose the best values according to real board stack up ?!
If you're referring to the impedance value you want to design to, this is specified in the standards for the high-speed interface on your component. For example, USB requires 90 Ohms differential impedance, which can be created using 2 traces each with 50 Ohms single-ended impedance. This example with USB is something I have discussed in other videos on routing USB in 2-layer PCBs.
@@Zachariah-Peterson Thanks a lot Mr. Peterson
Going back to Zafer Acun's original question ... I'm used to reading about 50-100 Ohms for PCB traces, and the ways to change it being things like trace width, distance to ground, maybe a different di-electric or thickness. These all seem like things the stackup manager would know about, and consider when targetting the intended 100 Ohms. I would expect some variation around vias and such, but getting to 250? Does that indicate a bug? Or at least a serious gap somewhere in the return path, or something else that should be flagged as a design error?
It's hard to say without looking at their design specifically. However I will say that I have seen this happen to me, and it occured because my layout did not match the line design I had calculated in the layer stack. The time I saw this was in a 4-layer RF board that had a portion of the layer stack cleared for a printed waveguide. The feedline was basically being routed over ground on the bottom layer because everything on the inner 2 layers was cleared. The line was sized to have ground 50 Ohms with ground on L2, not with ground on L4, so of course the impedance was through the roof and it was something like 230 Ohms.
@@Zachariah-Peterson That sounds like the sort of edge-case bug I could imagine writing, and it is good that the impedance checker calculates a different way as a cross-check.
@@jimjjewett There is already a simple solution for it though. If you have an impedance profile that has a the reference set to a specific layer (such as L2), then you can apply that profile in the Return Path rule. It should then check if you deviate from that reference layer and it would flag an error.
We have the same problem. Could it be that all layers are setup as signal layers instead of planes even if they are full of ground pour?
That might be the problem, an earlier comment made that point. In this test board the reference layers are defined as planes, as can be seen at 6:11.
I had been (perhaps wrongly?) assuming that impedance and Er were similar, and that in addition to reducing the _amount_ of current that flows through, higher impedance (or Er values) would also reduce the _speed_ of propagation. Therefore, the path's average impedance should be weighted not by length, but by time-spent-in-this-section, which would be something like length * impedance, and would therefore mean that sections with higher impedance change the average more than sections with lower impedance.
Are my model/assumptions just wrong? Or is that what Altium actually does, but it was too complex to explain in this video? Or is it just that this effect is typically small enough to ignore?
Higher Er means larger refractive index, which means lower speed of light (signal speed). In my opinion they should not do any weighted average, but instead they should show the characteristic impedance and input impedance along each section of the route as a heatmap. Sigrity does it and SIWave does it, so Altium should do it. They have all of the computational power built into the tool already, so it should not be any issue to display that result directly in the PCB editor other than maybe adding a new Panel. If you are going to show a single value as a weighted average, then you could certainly use the time delay in each section as the weight but I don't know that it communicates the impedance information in a new way that is intuitive, maybe I'm wrong though and would have to think about it. If the Er value is the same in all dielectrics in the layer stack then the two weighted averages are equal because the speeds should be equal in all layers except surface layers.
@@Zachariah-Peterson When a standard specifies 50 Ohm, does the "50" actually matter except at the connections? I'm inclined to think in software terms, so that the within-my-own-component impedance (and average impedance, and even variations in impedance) are irrelevant -- so long as the frequency-specific Voltage, Current, and Impedance are somehow correct at the endpoints, but ... I might be missing even something trivial.
@@Zachariah-Peterson Is this implicitly saying that (1) if you have anything beyond 4 layers, impedance controlled traces should get to a via immediately, and spend their time on inner layers (2) if you have 4 layers or less, then in practice, your constraints probably aren't tight enough to worry about this level of detail?
@@jimjjewett The 50 Ohms matters at the connection in terms of the input impedance. That's why impedance transformers and stubs work so well at specific frequencies with narrow bandwidth. But remember the input impedance is related to the line impedance, so it's not just a case that we can say the input impedance plays no role.
@@jimjjewett Getting to the via immediately from the chip output is not an expectation unless you are working at very high frequencies. The layer count doesn't matter so much at that point, what matters is the frequency compared to the distance spanned by the via, that via could be through-hole or blind/buried. For example, it's common to see RF signal launches that pass directly to L3 (through blind/buried via) from a connector or ball out on a component, and they work well up to 90 GHz. If you have only 4 layers or less you could still have very tight constraints, again because of frequency.
Came late!