One of the best instruction videos on actually learning the details behind - the "magic" that Xilinx does with tools (Vivado, SDK, etc.). These tools hide lots of details once you try to do something that is not exactly like a simple demo and often leave you stranded as to what to do next. I have watched many videos but believe that I understand more now than with many other ones. Great job on presenting! Thanks.
Thanks for the video! But when you were explaining about the purpose of the interconnect I was wondering if we can have two M_GP ports from the zynq and connect each of them to one of the gpio IP core directly without the interconnect. In that case will there be a memory overlap issue or will the zynq itself just send the data to the either of the Master ports depending on the address
You cannot connect 2 GP ports directly to the same input. That is a multiple drive. You can connect 2 GP ports to the same input through an interconnect. So the interconnect acts like a multiplexer. The address of the peripheral from both GP ports will be the same, because the address is assigned to the peripheral not to the interconnect. From software when you access the peripheral, in this case also it will be going through only one of the GP ports. If you put 2 processors and connect both of them to the same peripheral through an interconnect (again u cannot directly connect), and try to access it at the same time, the interconnect will be doing the arbitration and the processors will be served one after the other. In this case also the address of the peripheral from both processor perspective will be the same.
@@TheVipinkmenon I tried that.But it seems FPGA is not receiving the input.My program was a simple decimal to led converter(ex :if i give 3 as an input 3 leds should glow.).I didn't add UART IP into the block.Is it because of that.?
Great video !!! I have implemented an algorithm in VHDL I need to pack the implemented RTL logic into custom IP then access the IP from the ARM processor using SDK. What and how do I need to design the IP, I am new to this custom IP development, I am not understanding what logic where to initialize in axi slave template file. Any lead would be appreciated.
Basically you need to map all the control signals to your logic to registers and connect the signals from those register to your IP. The data to your IP should be also mapped to a register address and connect those as input or directly connect an AXI stream interface. You can check this video also for better idea th-cam.com/video/cz0iKv53Vww/w-d-xo.html
ThankYou Sir for the Video. It is really helpful. There is error when i try to Program my FPGA through SDK, "FPGA configuration is failed.DONE PIN is not High" . What is the FPGA Configuration that you have used?
FPGA configuration failed means FPGA programming (bitstream programming) failed. Usually happens if your cables are not properly connected or the configuration logic is in some error state. If configuration was successful, the done led will glow. If error is coming from SDK, try from Vivado also.
Great video but not sure why this is not working. I followed everything from Vivado to SDK got blue light after programmed. No LED is turning on. When I try a different value from A5 to FF and re-run I also get error "Memory Write Error at 0x10000. APB AP transaction error...". Any idea?
![[Full Episode] MasterChef Junior Thailand มาสเตอร์เชฟ จูเนียร์ ประเทศไทย Season 3 Episode 6](http://i.ytimg.com/vi/CVUx09Rx0-M/mqdefault.jpg)
One of the best instruction videos on actually learning the details behind - the "magic" that Xilinx does with tools (Vivado, SDK, etc.). These tools hide lots of details once you try to do something that is not exactly like a simple demo and often leave you stranded as to what to do next. I have watched many videos but believe that I understand more now than with many other ones. Great job on presenting! Thanks.
Thanks! This is really helpful for understanding these programs.
Yet again a great tutorial. Thank you very much.
Great tutorial! Great thanks! Very informative
Thanks for the video! But when you were explaining about the purpose of the interconnect I was wondering if we can have two M_GP ports from the zynq and connect each of them to one of the gpio IP core directly without the interconnect. In that case will there be a memory overlap issue or will the zynq itself just send the data to the either of the Master ports depending on the address
You cannot connect 2 GP ports directly to the same input. That is a multiple drive. You can connect 2 GP ports to the same input through an interconnect. So the interconnect acts like a multiplexer. The address of the peripheral from both GP ports will be the same, because the address is assigned to the peripheral not to the interconnect. From software when you access the peripheral, in this case also it will be going through only one of the GP ports. If you put 2 processors and connect both of them to the same peripheral through an interconnect (again u cannot directly connect), and try to access it at the same time, the interconnect will be doing the arbitration and the processors will be served one after the other. In this case also the address of the peripheral from both processor perspective will be the same.
@@TheVipinkmenon thanks a lot for the clarification!
what to do when there are 4 leds on the board.. (Xil_Out4 ?/)
Is it possible to use normal scanf function to give inputs to the board from the sdk terminal?
Yes. Just include stdio header
@@TheVipinkmenon I tried that.But it seems FPGA is not receiving the input.My program was a simple decimal to led converter(ex :if i give 3 as an input 3 leds should glow.).I didn't add UART IP into the block.Is it because of that.?
@@sarankk886 Can you post your code here? Just print something on the screen first to make sure the communication path is ok.
I am using Zybo Z7-10 board which have 4 LEDs (4-bits)... In this case how can I light up the LEDs? I think there is no function like Xil_Out4...
I am sure you have figured out the answer by now. In case you haven't, I just used Xil_Out8 and accessed the LEDs through the lower nibble.
Great video !!! I have implemented an algorithm in VHDL I need to pack the implemented RTL logic into custom IP then access the IP from the ARM processor using SDK. What and how do I need to design the IP, I am new to this custom IP development, I am not understanding what logic where to initialize in axi slave template file. Any lead would be appreciated.
Basically you need to map all the control signals to your logic to registers and connect the signals from those register to your IP. The data to your IP should be also mapped to a register address and connect those as input or directly connect an AXI stream interface. You can check this video also for better idea th-cam.com/video/cz0iKv53Vww/w-d-xo.html
ThankYou Sir for the Video. It is really helpful. There is error when i try to Program my FPGA through SDK, "FPGA configuration is failed.DONE PIN is not High" . What is the FPGA Configuration that you have used?
FPGA configuration failed means FPGA programming (bitstream programming) failed. Usually happens if your cables are not properly connected or the configuration logic is in some error state. If configuration was successful, the done led will glow. If error is coming from SDK, try from Vivado also.
@@TheVipinkmenon I could do it Sir, Thanks
@@TheVipinkmenon Sir, Is There a specific reaaon to use Vivado 2017.4 ?
I am getting error on something like mem error of APB 000000f or smthnf
same..
Great video but not sure why this is not working. I followed everything from Vivado to SDK got blue light after programmed. No LED is turning on. When I try a different value from A5 to FF and re-run I also get error "Memory Write Error at 0x10000. APB AP transaction error...". Any idea?
Under run configurations check Run ps7_post_config also. If AP transaction error comes always power cycle the board (power off and on)
@@TheVipinkmenon
Thank you that worked.
@@TheVipinkmenon thank you sir
Worked for me as well. Thank you so much!