An Introduction to FPGAs: Architecture, Programmability and Advantageous

#FPGAs, #Xilinx #ReconfigurableComputing
This is an introductory Video on the internal architecture of FPGAs, especially Xilinx FPGAs, and shows you how they achieve their reprogrammability.

[@dtwitchell456]

This is by far the best explanation I've ever seen, especially for a beginner like me

[@sidharth2261]

one of the best video series on FPGA programing. according to me

[@abdulah.malikkk]

Your content is extremely transformative for me. Can't thank you enough!

[@sree6119]

It’s really a great content sir, explained very well. Worth watching your videos.you saved my time in exploring about FPGA as for my PhD research ,I need to work on FPGA.

[@kayitbilgileri]

Wonderful explanation. Great work. Thank you very much. I hope you will continue this content in a very near future again.

[@kanchanareddy418]

Thank you so much for the content explained in detail, very well understood

[@ravitejab2095]

Heartfully say it is very good explanation

[@ElectroniTechInsights]

Sir very nice content and explanation, its really needful for me thank you.

[@peterlin2352]

Very excellent presentation!

[@nambininrakotojaona6183]

good explanation

[@teer3702]

Hello Sir,
First, I would like to thank you for uploading these videos, these are very useful. Sir, You are a very good teacher. Can I get your lecture videos from other subjects?

[@ravitejab2095]

Excellent

[@mohammed_mairajuddin_musharraf]

My most productive 48 minutes 32 seconds.

[@Sadiqkhan-st4pt]

Great content.
Can you please introduce yourself as well? I think I am one of your fans. :)

[@TheVipinkmenon]

Thanks. This is my background. vipinkizheppatt.github.io/

[@sandunranasinghe3444]

Dear Vipin, Thank you for the course. I am following the course. I have a question. I am using the xilinx ISE 14.7 software which works on oracle VB. I could not program the FPGA as I cannot detect any port of Xilinx SDK terminal. I have tried the following. 1. Installing cable drivers. (C:\Xilinx\Vivado\2022.2\data\xicom\cable_drivers
t64) -> Install_drivers as admin.
2. Tries to uninstall exiting drivers and reinstall them.
3. Tried to add myself to dialout group
In the process, of installing cable drivers, I received following message. (INFO: InstallPath="C:\Xilinx\Vivado\2022.2\data\xicom\cable_drivers
t64\"
windrvr6 is not installed (this is expected for Windows 10 and later))
I am sure the windows 10 does have that driver. Do you have any idea about the issue? Please let me know. Thanks!

[@ranitapaul29]

will the Verilog code be exactly same for designing spi controller for arty-z7 board ? Arty-z7 board doesn't have oled display

[@ElectroniTechInsights]

With the help of MATLAB how we can start learning FPGA , please give me your guidance on this.
Thankyou.

[@huojinchowdhury3933]

How input say 00 knows that it needs to access first location of the LUT? Is it anything we need to mention while programming? And how can we store any logic gates truth table's output in LUT?

[@TheVipinkmenon]

LUTs are small memories and they are made like that. 00 is always first location 01 second etc. What value should be stored in location 00 depends on what we want to implement. Now a days we don't directly specify it. We write the logic in an HDL language and the FPGA vendor provided software will find what values to be stored

[@huojinchowdhury3933]

@@TheVipinkmenon My fpga board have 6 input and 2 output LUT. What I will get output for input 000000. Here, I can get two output. What I will get first and second output?

[@TheVipinkmenon]

From Virtex 6, Xilinx uses 6 input LUTs. Those LUTs have 2 outputs. You can use a LUT as a 6 input 1 output LUT or 2 five inputs 2 output LUTs as the LUTs are fracturable. You can't use it as a 6 input 2 output LUT. Details you can see here. www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf. Please read chapter 1.

[@huojinchowdhury3933]

@@TheVipinkmenon Can you tell me how can I configure 6 input 1 output LUT for half adder? truth table of half adder has two output. One for carry and other for sum

[@huojinchowdhury3933]

@@TheVipinkmenon It is for educational purpose. And I need to get high performance. So, I need to understand in very basic layer. How simple one bit addition operation can be performed using CLB?

[@christiangrenier9434]

In FPGA I heard about slices, what is it exactly?

[@ayasaad1856]

can I have the source of the presentation, please?

[@alexandrosiii5676]

Hello
Vipin Kizheppatt. Can you send me all zedboard related slides?

[@pradeepkumarreddy4651]

sir can you add hbm in vivado tutorial