Thanks. Yeah, the 27c322 is a pain to program, but it makes life so much easier! Some good twists coming up later in the series. Should be about 5-6 videos in total.
WOW! I absolutely love this! And I was so pleased to see all those Ground signals on the data bus connector. So many DIY projects don't have enough and suffer from ground-bounce and other issues. I have followed a fair chunk of your earlier work, so everything here made complete sense to me. I can't wait to see how it all comes together.
Hi Martin, Yep, the 138s were good for the old system, but i'm redesigning the register bank, so i don't think i'll need them for this build. I'm trying a slightly shorter format, what do you think?
@@DrMattReganI liked it. I think ten to fifteen minutes is a good sweet spot for these sort of videos. Longer technical videos can be harder to find the required uninterrupted block of time, so they often languish in my watch later list.
Really enjoying all of these playlists (looking forward to the next in this series a LOT!) - thanks for all the hard work. Im curious why you decided to brake the design down into 2 identical blocks and not 4. I would expect to either copy and paste 4 times and print 1 board, or just have 1 EEPROM/Flip-Flip and print 4 boards.
Glad you enjoy it! Good question. I want to use the same EPROM boards for a Turing6502 version of the machine which only has 2 EPROMs. Next one is sitting on the hard-drive, i just have a little more debug to do.
Just found you. Great tool for demonstrating processor concepts. Subscribed & liked. Looking forward to your development "notes". And thank you for sharing this.
Very nice, I was thinking of the elimination of sequence counter by having the "next microinstruction address" encoded in the microcode itself as I was watching the video, but thought it won't happen because you didn't have enough data lines - you fixed that by going to larger ROM's ;-) Will allow to do some nice looping and jumping state machine tricks most likely :-)
Love this! Am I crazy to think that it would be nice to ultimately have an "alternate" "6502 board" to replace the TTL circuits, to make a simpler build?
Unfortunately I'm crap at keeping secrets, so the chip count will get pretty low without having to use a 6502. The 6502 is pretty opaque, but the idea behind this build it to be be completely transparent. You'll know every detail of how it works.
Yep, it was called the SAP-1. In some ways, this series is to fill the gap between Ben Eaters 8-bit computer series (SAP-1)and his 6502 series. If you want to see more, have a look at the SAP-6502 series.
In my processor's design, I prefer to use two bits (M and L, after most/least) to code sequence jumps, and a simple decoder made of four NAND gates, to code: • no jump (ML=00}, • jump if flag clear (ML=01), • jump if flag set (ML=10), and • jump nomatterwhat (ML=11). If someone wants to try, the description of the simple decoder is as follows: Components: • Three 2-inputs NAND gates with inputs N1a, N1b, N2a, N2b, N3a, N3b and outputs N1o, N2o, N3o; • One 3-inputs NAND gate with inputs N4a, N4b, N4c, and output N4o. Connections: /* Fourth gate inputs are the three other gates' outputs N1o - N4a N2o - N4b N3o - N4c /* Inputs to the three first gates: F - N1a /* See F below M - N1b M - N2a L - N2b L - N3a !F - N3b /* See !F immediately below. Where F is the non-inverted output from the flags multiplexer and, !F, the inverted one; none of them go to any of the ROM address lines. Now that the decoder is internally connected, its output, N4o, is connected to the Load Syncronous input of a sequencer, its parallel load inputs to 5 lines of microinstruction representing the jump-to sequence number. If no counter is used, as Dr. Matt shows, these jump-to bits must be different from the normal next sequence number, and the N4o should drive a 5-bits multiplexer to use jump-to sequence number when high, next sequence number when low. With this method, microroutines gain the same kind of flow control as assembler programs, with loops and conditional branching, and, therefore, there's no need to have several microroutines per instruction: one with jumps (if at all, most won't need more jumps than going to the microroutine's end section when done) will do. These jumps can coexist with other actions in their microinstruction, they don't require a dedicated one. Edited: word mistake correction ('that' --> 'as')
Yes I think you've already predicted (and implemented) where I'm going with this (well done). This instruction count becomes a finite state machine and eventually we only need one copy of the various microinstruction routines.
@@DrMattRegan I've used a vertical microinstruction architecture to have up to six simultaneous microactions in 32 bits. It's not slower: after fetching a microinstruction, its transparent latch is delatched and starts decoding while last microinstruction cycle's data ends being processed, then relatched to memorize the new microinstruction, moment when just-processed data is latched too in its registers or written to memory (delatched when the microinstruction was). A three-phase clock can do, even a two-phase one can if the said delatching is advanced to sequence-counting phase. Decoding just takes place during delayed data processing, but it still processes data one cycle at a time.
@@DrMattRegan I did, yes, but not with much interest, as I learned practically all about Turing machines half a century ago, when becoming a teenager, in the first technical book I bought: B. A. Trachtenbrot's "Theory of Computation Machines," is how I'd translate its title from my language. I knew nothing of algebra then, but much of the book was on words algebra. Also a good section, on number theory and their equivalence to computation. Yet I read it all several times.
This project is crazy, but also the easiest discrete 6502 design out there. I wish you would open source the TTL Apple 2 computer, I would like to build one for myself.
@@DrMattRegan Thanks for your work. I hope you can open the whole project including the rom files so that I can actually build a sap6502 or sapz80 exactly like the one in your video, I really want to build an Apple 2 or ZX using TTL+ROM.😄
No, the output format is complete arbitrary and designated by me. I have a large set of #define's in the microcode generator that determines what each bit does.
@@DrMattRegan i thought it would of been a set format on the frame that is used generally but yeah this is another complex issue at hand if everyone is working to their standards and computer doesn't understand other types of interpretation when connected to www my brain is overclocking now. 🤔😅
It is possible to use a single EPROM if you look at: th-cam.com/play/PLjQDRjQfW-84aOLT33kzoZghRofK-uL1F.html But for now I'm sticking close to SAP1 design.
Couple of reasons. First, I already have th-cam.com/play/PLjQDRjQfW-85BWo4IC3WYUDZ-hC8qJsqO.html Second reason is that I think you get more insight into microprocessors by building them (and watching them be built) rather than just using them IMHO
With the EEPROMs having 21 address lines, do you still need the flag multiplexor? Could we not instead supply the EEPROM address lines with the Instruction (8 bits), Step (5 bits) and Status register (7+1 bits)? Im sure Im missing something here but thought it would be worth asking :D
Yes, you could probably get away without the flag multiplexer, but i wasn't keen to change the microcode from the youtube series on the microcode. th-cam.com/video/FtNb4VWd9dM/w-d-xo.html Ultimately, i do plan to use the entire address space (at least 20 bits), want to guess how?
Well i do like pipelining... Here is an old paper i wrote on the matter. dl.acm.org/doi/pdf/10.1145/192161.192192 but for a beginner/intermediate series, it just adds unnecessary complexity. That said i do plan on a 2 stage pipeline in the Turing6502, which is what this series will evolve into.
Welcome. Depends a bit on the speed of the memories. I should be able to clock it at 5MHz, but it requires 2-3x the clocks per instruction, so it will probably end up about 1-2x faster. I may have to slow it down through the microcode to get the timing more accurate.
why a tll 6502...? its a down grade the problem is this vintage computer....has some custom chips. isay that you make a magnificent work to clone the ii...... and i watch all the episodes.....nice.....
LoL. There was was no massive integration in the Apple 2..it was already made from discrete TTL parts. Why? Because in those days field programmable devices such as PLD's, CPLD's, FPLS, PAL's, FPGA's hadn't even been invented.
@@deang5622think you've completely missed the point of the entire video series. The aim is to build a discrete cpu that is functionally the same as the 6502.
@@deang5622 Me personally, I think it's better to use discrete because you can understand how it functions a bit better, and modern devices are like black magic compared to this.
Brilliant series in the making. Fabulous idea, can't wait to see how it pans out.
Oh and the infamous 27C322 with its 42 pins in DIL! :)
Thanks. Yeah, the 27c322 is a pain to program, but it makes life so much easier! Some good twists coming up later in the series. Should be about 5-6 videos in total.
More please, I wanted it all... ❤
WOW! I absolutely love this! And I was so pleased to see all those Ground signals on the data bus connector. So many DIY projects don't have enough and suffer from ground-bounce and other issues. I have followed a fair chunk of your earlier work, so everything here made complete sense to me. I can't wait to see how it all comes together.
Glad you like it. Intermitted electrical issues are the worst. I have a nasty timing issue coming up soon.
This is amazing. I have wanted to make an Apple || clone for a long time. Thank you for doing this!
Thanks. It gets pretty interesting - stay tuned.
I really need to thank TH-cam’s algorithm for recommending me this hidden gem.
Great job, keep it up!
Thanks. Enjoy.
love it, looking forward to following this series!
Thanks Paula. I’m keen to hear what other TTL CPU builders think.
@@DrMattRegan It looks fab in that clear case, and I'd be up for making one when you're ready to share schematics/PCBs/etc.
Using the 138 decoders to select the IC driving the W bus is a really good idea. I hadn't appreciated that in your prior videos.
Hi Martin, Yep, the 138s were good for the old system, but i'm redesigning the register bank, so i don't think i'll need them for this build. I'm trying a slightly shorter format, what do you think?
@@DrMattReganI liked it. I think ten to fifteen minutes is a good sweet spot for these sort of videos. Longer technical videos can be harder to find the required uninterrupted block of time, so they often languish in my watch later list.
I will defenetly follow this series and try to build my own, this is very interesting!
Excellent. Enjoy!
I’m looking forward to this series! Great stuff!
This is going to be fun
Really enjoying all of these playlists (looking forward to the next in this series a LOT!) - thanks for all the hard work.
Im curious why you decided to brake the design down into 2 identical blocks and not 4.
I would expect to either copy and paste 4 times and print 1 board, or just have 1 EEPROM/Flip-Flip and print 4 boards.
Glad you enjoy it! Good question. I want to use the same EPROM boards for a Turing6502 version of the machine which only has 2 EPROMs. Next one is sitting on the hard-drive, i just have a little more debug to do.
Just found you. Great tool for demonstrating processor concepts.
Subscribed & liked.
Looking forward to your development "notes".
And thank you for sharing this.
Excellent. Welcome. Hope you find it interesting.
Fantastic... Hello from Brazil.
Hey, thanks! Great to hear from you!
oooo very cool. I like this
Wow..this is totally awesome.. I'm ready to start the journey.. let's begin...❤
All the best
Very nice, I was thinking of the elimination of sequence counter by having the "next microinstruction address" encoded in the microcode itself as I was watching the video, but thought it won't happen because you didn't have enough data lines - you fixed that by going to larger ROM's ;-) Will allow to do some nice looping and jumping state machine tricks most likely :-)
Yep, it really opens things up a bit. Glad you're enjoying it.
Nice, can't wait to see it working!
You and me both!
This is amazing!!!! Subscribed
Glad you are enjoying it.
Nice job! It needs a big schematic and block diagram to appreciate.
Love this! Am I crazy to think that it would be nice to ultimately have an "alternate" "6502 board" to replace the TTL circuits, to make a simpler build?
Unfortunately I'm crap at keeping secrets, so the chip count will get pretty low without having to use a 6502. The 6502 is pretty opaque, but the idea behind this build it to be be completely transparent. You'll know every detail of how it works.
I built Ben’s 8-bit a couple winters ago, fantastic experience, didn’t even know it had a name. SAP-1?
Yep, it was called the SAP-1. In some ways, this series is to fill the gap between Ben Eaters 8-bit computer series (SAP-1)and his 6502 series. If you want to see more, have a look at the SAP-6502 series.
That’s nuts!
Enjoy!
In my processor's design, I prefer to use two bits (M and L, after most/least) to code sequence jumps, and a simple decoder made of four NAND gates, to code:
• no jump (ML=00},
• jump if flag clear (ML=01),
• jump if flag set (ML=10), and
• jump nomatterwhat (ML=11).
If someone wants to try, the description of the simple decoder is as follows:
Components:
• Three 2-inputs NAND gates with inputs N1a, N1b, N2a, N2b, N3a, N3b and outputs N1o, N2o, N3o;
• One 3-inputs NAND gate with inputs N4a, N4b, N4c, and output N4o.
Connections:
/* Fourth gate inputs are the three other gates' outputs
N1o - N4a
N2o - N4b
N3o - N4c
/* Inputs to the three first gates:
F - N1a /* See F below
M - N1b
M - N2a
L - N2b
L - N3a
!F - N3b /* See !F immediately below.
Where F is the non-inverted output from the flags multiplexer and, !F, the inverted one; none of them go to any of the ROM address lines.
Now that the decoder is internally connected, its output, N4o, is connected to the Load Syncronous input of a sequencer, its parallel load inputs to 5 lines of microinstruction representing the jump-to sequence number. If no counter is used, as Dr. Matt shows, these jump-to bits must be different from the normal next sequence number, and the N4o should drive a 5-bits multiplexer to use jump-to sequence number when high, next sequence number when low.
With this method, microroutines gain the same kind of flow control as assembler programs, with loops and conditional branching, and, therefore, there's no need to have several microroutines per instruction: one with jumps (if at all, most won't need more jumps than going to the microroutine's end section when done) will do. These jumps can coexist with other actions in their microinstruction, they don't require a dedicated one.
Edited: word mistake correction ('that' --> 'as')
Yes I think you've already predicted (and implemented) where I'm going with this (well done). This instruction count becomes a finite state machine and eventually we only need one copy of the various microinstruction routines.
@@DrMattRegan I've used a vertical microinstruction architecture to have up to six simultaneous microactions in 32 bits. It's not slower: after fetching a microinstruction, its transparent latch is delatched and starts decoding while last microinstruction cycle's data ends being processed, then relatched to memorize the new microinstruction, moment when just-processed data is latched too in its registers or written to memory (delatched when the microinstruction was). A three-phase clock can do, even a two-phase one can if the said delatching is advanced to sequence-counting phase. Decoding just takes place during delayed data processing, but it still processes data one cycle at a time.
@@wafikiri_ out of interest, have you watched the Turing6502 videos?
@@DrMattRegan I did, yes, but not with much interest, as I learned practically all about Turing machines half a century ago, when becoming a teenager, in the first technical book I bought: B. A. Trachtenbrot's "Theory of Computation Machines," is how I'd translate its title from my language. I knew nothing of algebra then, but much of the book was on words algebra. Also a good section, on number theory and their equivalence to computation. Yet I read it all several times.
This project is crazy, but also the easiest discrete 6502 design out there. I wish you would open source the TTL Apple 2 computer, I would like to build one for myself.
Working on it. The schematics are being developed under this playlist.
@@DrMattRegan Thanks for your work. I hope you can open the whole project including the rom files so that I can actually build a sap6502 or sapz80 exactly like the one in your video, I really want to build an Apple 2 or ZX using TTL+ROM.😄
I am interested in how this output frame works is it built in frame or is this something you set at 3:59 time stamp
No, the output format is complete arbitrary and designated by me.
I have a large set of #define's in the microcode generator that determines what each bit does.
@@DrMattRegan i thought it would of been a set format on the frame that is used generally but yeah this is another complex issue at hand if everyone is working to their standards and computer doesn't understand other types of interpretation when connected to www my brain is overclocking now. 🤔😅
Is it not better to use in the controlling logic one large eprom plus some demuxes instead of 5 eproms?
It is possible to use a single EPROM if you look at:
th-cam.com/play/PLjQDRjQfW-84aOLT33kzoZghRofK-uL1F.html
But for now I'm sticking close to SAP1 design.
Is there any reason why you don’t use the 6502?
Couple of reasons. First, I already have th-cam.com/play/PLjQDRjQfW-85BWo4IC3WYUDZ-hC8qJsqO.html
Second reason is that I think you get more insight into microprocessors by building them (and watching them be built) rather than just using them IMHO
With the EEPROMs having 21 address lines, do you still need the flag multiplexor?
Could we not instead supply the EEPROM address lines with the Instruction (8 bits), Step (5 bits) and Status register (7+1 bits)?
Im sure Im missing something here but thought it would be worth asking :D
Yes, you could probably get away without the flag multiplexer, but i wasn't keen to change the microcode from the youtube series on the microcode. th-cam.com/video/FtNb4VWd9dM/w-d-xo.html
Ultimately, i do plan to use the entire address space (at least 20 bits), want to guess how?
@@DrMattRegan Hmm - Im _way_ out of my depth here, but as a guess ... pipelining?
Well i do like pipelining... Here is an old paper i wrote on the matter.
dl.acm.org/doi/pdf/10.1145/192161.192192
but for a beginner/intermediate series, it just adds unnecessary complexity. That said i do plan on a 2 stage pipeline in the Turing6502, which is what this series will evolve into.
@@DrMattRegan Neat - I look forward to that.
If not pipelining, what are the 7 EPROM address bits going to be used for?
Have a look here -
th-cam.com/play/PLjQDRjQfW-84j-jLvrbEeDvGl0QrhX9p7.html
Newbie question: Will these changes limit the clock speed?
Welcome. Depends a bit on the speed of the memories. I should be able to clock it at 5MHz, but it requires 2-3x the clocks per instruction, so it will probably end up about 1-2x faster. I may have to slow it down through the microcode to get the timing more accurate.
Very cool! @@DrMattRegan
how can we contact you?
Easiest was is drmatthewregan AT gmail DOT com
why a tll 6502...? its a down grade
the problem is this vintage computer....has some custom chips. isay that you make a magnificent work to clone the ii...... and i watch all the episodes.....nice.....
You might like this playlist instead
th-cam.com/play/PLjQDRjQfW-85BWo4IC3WYUDZ-hC8qJsqO.html
LoL. There was was no massive integration in the Apple 2..it was already made from discrete TTL parts.
Why? Because in those days field programmable devices such as PLD's, CPLD's, FPLS, PAL's, FPGA's hadn't even been invented.
Well, yes. That is why I chose the apple2, but CPU in the Apple isn't made from discrete TTL parts.
@@DrMattRegan I think it's far better to teach modern devices and design techniques than build an MSI IC out of simpler discrete logic.
@@deang5622think you've completely missed the point of the entire video series. The aim is to build a discrete cpu that is functionally the same as the 6502.
@@deang5622 Me personally, I think it's better to use discrete because you can understand how it functions a bit better, and modern devices are like black magic compared to this.