In complex designs like 20 layer or 26 layers boards for exmaple, with USB 90ohms + DDR4 with 50 ohms + GDDR6 with 45 ohms + PCIE with 100ohms its impossible to work just in controlled impedance. And you can add either a 100GBs PAM4 link with 20 cm long, that need more width due to the DC losses but still need to match the 100 ohms impedance :)
I agree to an extent, if you just segment those different impedance onto different layer sets then you could probably make it work in conjunction with testing from your manufacturer, but I think that is impractical and might leave you a lot of space on those layers that are allocated to specific impedances. You might have better luck doing controlled impedance with mixes of differential and single-ended but only with widely spaced differential pairs because the odd-mode impedances will be very close to the single-ended impedances. In that case you might be able to do 45 Ohms GDDR6 and a 90 Ohms differential interface on the same layer and you could do controlled impedance as long as the USB lines are not very closely coupled together. Regardless, I prefer controlled dielectric anyways.
Hi Zach, in your example @12:32 you mentioned that *50 ohm impedance required for 5 mil wide traces on layer 1and 4. I assume you are using co planner since no frequency is mentioned, the GND is layer 2, so how it is possible to establish 50 ohm on layer 1 and 4 reference to GND with the same 5 mil width since there is a core +prepreg between layer 4 and GND while just a prepreg between layer 1 and GND? is it that Dk for top prepreg = Dk core + lower prepreg? thanks and have a nice weekend :)
the only possible way "I think" is to use the ground pour on the L03_PWR as a reference for the RF signals on layer 4 while avoiding any RF traces located over a power trace as well as to utilize L02_GND as a reference for the RF signals on layer 1. personally i don't recommend such a solution
@@hazehh789 Three things to note here: 1) In this example it was not meant to be coplanar, but you could do it as coplanar. If we ignore the layer names then doing this as the other reply mentioned would be fine. 2) You can do it also with L3 PWR as a reference plane as well, but it's not preferred because you would assume that, at some point, you might have to route those impedance controlled traces between L4 and L1, so then you have to put stitching vias around those signals and GND pours on L4 (large clearance for pours on L4). When I've done this type of stackup, it's been done for something that has digital stuff on the L1 side, but it also needs a lot of power; they are not common. In those boards I would just route slower control signals and miscellaneous components on L4. 3) Just because you state there is an impedance requirement on both L1 and L4 does not mean you have to actually use it, you could only place the impedance controlled signals on L1. The statement in the drawing reflects the symmetry of the stackup.
TIL I've basically been doing controlled dielectric design while calling it controlled impedance. I tend to pick dielectric thickness/Dk based on the general widths I want my traces to have depending on clearance constraints or design requirements, then simulate/calculate to verify them and give the fab house both the full stackup table AND an impedance table in case they have substitutes/suggestions.
That's something I've always noticed, people using "controlled dielectric" and "controlled impedance" interchangeably, there is also someone I know who used "controlled stackup" to refer to controlled dielectric. My EMS clients generally require an impedance table even if doing controlled dielectric, but I stopped giving that table to other fabs I work with when we're running production, as soon as they see it they immediately assume I want impedance testing added to the order.
Thanks a lot ❤
In complex designs like 20 layer or 26 layers boards for exmaple, with USB 90ohms + DDR4 with 50 ohms + GDDR6 with 45 ohms + PCIE with 100ohms its impossible to work just in controlled impedance. And you can add either a 100GBs PAM4 link with 20 cm long, that need more width due to the DC losses but still need to match the 100 ohms impedance :)
I agree to an extent, if you just segment those different impedance onto different layer sets then you could probably make it work in conjunction with testing from your manufacturer, but I think that is impractical and might leave you a lot of space on those layers that are allocated to specific impedances. You might have better luck doing controlled impedance with mixes of differential and single-ended but only with widely spaced differential pairs because the odd-mode impedances will be very close to the single-ended impedances. In that case you might be able to do 45 Ohms GDDR6 and a 90 Ohms differential interface on the same layer and you could do controlled impedance as long as the USB lines are not very closely coupled together. Regardless, I prefer controlled dielectric anyways.
Hi Zach, in your example @12:32 you mentioned that *50 ohm impedance required for 5 mil wide traces on layer 1and 4. I assume you are using co planner since no frequency is mentioned, the GND is layer 2, so how it is possible to establish 50 ohm on layer 1 and 4 reference to GND with the same 5 mil width since there is a core +prepreg between layer 4 and GND while just a prepreg between layer 1 and GND? is it that Dk for top prepreg = Dk core + lower prepreg? thanks and have a nice weekend :)
I'm assuming the design utilized Power+Signal on surface layers and GND in internals, making L1-L2 and L3-L4 impedance profiles symmetrical.
the only possible way "I think" is to use the ground pour on the L03_PWR as a reference for the RF signals on layer 4 while avoiding any RF traces located over a power trace as well as to utilize L02_GND as a reference for the RF signals on layer 1. personally i don't recommend such a solution
you're right, I completely missed the layer names.
@@hazehh789 Three things to note here:
1) In this example it was not meant to be coplanar, but you could do it as coplanar. If we ignore the layer names then doing this as the other reply mentioned would be fine.
2) You can do it also with L3 PWR as a reference plane as well, but it's not preferred because you would assume that, at some point, you might have to route those impedance controlled traces between L4 and L1, so then you have to put stitching vias around those signals and GND pours on L4 (large clearance for pours on L4). When I've done this type of stackup, it's been done for something that has digital stuff on the L1 side, but it also needs a lot of power; they are not common. In those boards I would just route slower control signals and miscellaneous components on L4.
3) Just because you state there is an impedance requirement on both L1 and L4 does not mean you have to actually use it, you could only place the impedance controlled signals on L1. The statement in the drawing reflects the symmetry of the stackup.
@@Zachariah-Peterson thanks for explaining
Thanks a lot Zack! It’s very useful video. You make always brilliant work.🙏
Hi Zach! great job as ever. I think I can not encounter a topic you have explained that I already known :)
TIL I've basically been doing controlled dielectric design while calling it controlled impedance.
I tend to pick dielectric thickness/Dk based on the general widths I want my traces to have depending on clearance constraints or design requirements, then simulate/calculate to verify them and give the fab house both the full stackup table AND an impedance table in case they have substitutes/suggestions.
That's something I've always noticed, people using "controlled dielectric" and "controlled impedance" interchangeably, there is also someone I know who used "controlled stackup" to refer to controlled dielectric. My EMS clients generally require an impedance table even if doing controlled dielectric, but I stopped giving that table to other fabs I work with when we're running production, as soon as they see it they immediately assume I want impedance testing added to the order.
For those control freaks out there - controlled impedance is much more flexible and the designer remains in control.
I always go controlled dielectric/stackup because I am a control freak LOL
@@Zachariah-Peterson Each to their own!