How to run Linux on RISC-V with open hardware and open source FPGA tools

by Drew Fusitni
At: FOSDEM 2020
video.fosdem.o...
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
This talk is a replacement for Jasper Nuyens' cancelled "FreedomEV 2.0" talk, as Jasper decided to not attend FOSDEM20.
Room: K.4.401
Scheduled start: 2020-02-02 10:00:00

[@leosmi1]

Ohhhmmmmmmm looks like a meditation session

[@eagledee7753]

Thank you very much for all the info and keep the good work.

[@parrotraiser6541]

The original "green card" was for the IBM 360 instruction set. Essential for debugging COBOL core dumps. It was changed to yellow when the 370 was introduced.
What would be the problems in of replacing an ARM chip with a RISC-V on an existing board, (the Rapsberry Pi being the obvious candidate), or cloning one for location of peripherals and other physical attributes ? The nature and number of connections (pins in and out)? Missing or additional features, (e.g. device controllers)? Exploiting the existing ecosystem for things like cases and cooling would let effort be concentrated on the areas that matter.

[@------country-boy-------]

Running Debian on a Raspi 3b. It came with the Bookshelf app in the main menu that provides links to all the Hackspace, Magpi and Wireframe magazines along with lots of programming books. i must officially be a nerd. Sometimes i wonder how it could be possible to design software to run parallel so that clock frequencies would not need to be increased. I look forward to when NVIDIA reveals how their GPUs parallel process data. That would be major step in the Open Source Community. Maybe the Raspberry Pi community already provides info on the GPU section of the CPU/GPU SOC and maybe it can be accessed. I need to look into it. Long Live Linux and the RISC Team !!!!

[@aliuzel4211]

Thanks Drew.

[@davedaley9093]

When IBM released the System 360 part of the documentation was a trifold card with all the hardware instructions and instruction formats contained on it called The Programmer Reference Card. Later when the System 370 was released they produced the same sort of card for the new system but printed on yellow cardstock. All the programmers I knew still called the green card.

[@bennguyen1313]

I understand Risc-V has the advantage of a royalty-free instruction set, but does that mean each Risc-V implementation will have different performance (LUTs, etc), based on how one chooses to implement those instructions (ex. BrunoLevy / learn-fpga / FemtoRV vs clairexen / YosysHQ / picorv32 vs VexRISCV)? And would there be performance differences if implementing the same Risc_V on different vendor FPGAs? Or even just a different FPGA within the same family?
Also, if nmigen -> Amaranth HDL allows you to generate HDL from Python... is there any reason why the resulting verilog-2001 couldn't be synthesized onto any FPGA/CPLD (assuming it has the resources)? Microchip Smartfusion2? Or is there something specific that's required in the toolchain (Yosys+VPR/nextpnr)?
Also when using these newer open-source tools, how does one constrain the design , and create test-benches? Can this also done in python/scala, or do you need to use the vendor tool? I’m guessing debugging and single-stepping the risc-v code could use the standard eclipse/open-ocd?

[@VictorGallagherCarvings]

Up coming in 2020 ! When was this recorded ?

[@seuri678]

in video description:
Scheduled start: 2020-02-02 10:00:00

[@slickwillie3376]

Wassup? Maybe you can help me. I cannot register on Sifive. Please fix. Thanks.

[@antoniostorcke]

Will apps compiled for ARM run on RISC-V ?

[@Gunnl]

You could have at a minimum .. copied the man's name correctly ...

[@drywallguy87]

Ummmm

[@HeyItsSahilSoni]

Warning: do not read this if you don't want to ruin this video for you.
This guy says "umm.." a lot, like a lot a lot.
Throwing me off a bit once I noticed it..

[@nagrajnaik7288]

delete this!

[@ryanleemartin7758]

I h8 u

[@pedrophmg]

umm, i think that, umm, you might be, umm, exaggerating a little, umm...

[@TheKillerview]

Not cool man! Now I can't unhear it! Oh, and there's also the fact that they didn't drop a link with RISC-V's channel!

[@Gunnl]

I've had worst teachers...

[@RinksRides]

thinking this could have ben a 20 min video umm without all the umm interruptions umm try umm maybe scripting your umm presentation umm maybe next umm video umm i'll leave an umm like or umm subscribing umm Ill watch maybe umm the next video umm have a good day.

[@kevinclaypool6345]

You need to work on your public speaking skills. This...ummm .. was...ummm... Unbearable...ummmm