Semiconductor Memories : RAM - Memory Decoding Explained
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- เผยแพร่เมื่อ 29 มิ.ย. 2024
- In this video, how the Memory Decoding is carried out in the RAM (Random Access Memory) is explained in detail.
The following topics are covered in the video:
0:00 Introduction and Recap of the Previous Video
1:41 How the Read / Write Operations are Performed (Timing Diagram)
6:41 Logic Circuit of One Binary Cell in Memory
11:41 Logic Diagram of 16 x 4 RAM and Address Decoding in RAM
14:15 Co-incident Decoding
17:28 Address Multiplexing in RAM
20:51 Error Detection and correction in RAM (Breif Discussion)
22:21 Types of RAM
The link for the other useful videos related to memory and memory decoding:
1) Decoder Explained:
• Decoder Explained | Wh...
2) Error Detecting Code: Parity Bit
• Error Detecting Code :...
3) Hamming Code: Error Correcting Code
• How Hamming Code Corre...
4) SRAM vs DRAM
• SRAM vs DRAM : How SRA...
5) Types of DRAM
• Different Types of DRA...
6) Cache Memory:
• Cache Memory Explained
7) Semiconductor Memories: RAM
• Semiconductor Memories...
This video will be helpful to all the students of science and engineering in understanding Memory Decoding in RAM.
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Music Credit: www.bensound.com - วิทยาศาสตร์และเทคโนโลยี
The link for the other useful videos related to memory and memory decoding:
1) Decoder Explained:
th-cam.com/video/a3wh7xV5PBU/w-d-xo.htmlsi=EXXa757x8mijj5Fz
2) Error Detecting Code: Parity Bit
th-cam.com/video/Bwih7_AT1oI/w-d-xo.htmlsi=KBy4S5mymP-_xwPa
3) Hamming Code: Error Correcting Code
th-cam.com/video/t4kiy4Dsx5Y/w-d-xo.htmlsi=Jm-Mvz5ZoBmGQS05
4) SRAM vs DRAM
th-cam.com/video/r787m_IaR1I/w-d-xo.htmlsi=flXSh3EmNu1ko6-i
5) Types of DRAM
th-cam.com/video/DLM20pWqMyU/w-d-xo.htmlsi=z4jZUPkQsMZCDV9Q
6) Cache Memory:
th-cam.com/video/Zr8WKIOIKsk/w-d-xo.htmlsi=8HBGfJL5Ye4WEGw_
7) Semiconductor Memories: RAM
th-cam.com/video/a--rNdqtwCI/w-d-xo.html
Please make a video on column multiplexing for memory and how many muxs are required while folding the whole memory cell , i mean that how the aspect ratio can be reduced in memory cell.
Tough topics become sooo easy with your excellent technique of making video lectures 🎉👏🏻👏🏻
eğer bugün konuları bitirirsem you are my new crush.......
You're amazing... Love fom Bangladesh
Sir, what is the difference between the logic circuit of 1 binary cell and using SRAM Cell (7:58)?
At 14:43 it should be "k+1 inputs for each AND gate"
Thank you for these amazing videos.
The SRAM cell circuit is the actual circuit. That is how the 1 bit of information is stored in the SRAM. But here the circuit which I have shown for 1 binary cell is a logical circuit. That is a way of representing the same circuit in a logical way.
We need video about comm protocal LIKE UART SPI I2C Can Lin
Very very nice 🎉🎉
What is the difference between address multiplexing and coincident circuits ? 18:38
In coincident decoding, the decoding logic is divided into row and column decoder. Here, for both row and column decoding when we use same address lines using time multiplexing( rather than separate address lines) then that is called address multiplexing. I hope, it will clear your doubt.
how to cascade such 1 bit ram modules to obtain 2 x 8 ram memory module??
In the video, I have already shown how to design 16*4 RAM using 1 bit RAM module. If you watch the entire video you will get it.
Assembly language 8086
Please also provide the source of this information.
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You may use subtitles.
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