The link for the other useful videos related to memory and memory decoding: 1) Decoder Explained: th-cam.com/video/a3wh7xV5PBU/w-d-xo.htmlsi=EXXa757x8mijj5Fz 2) Error Detecting Code: Parity Bit th-cam.com/video/Bwih7_AT1oI/w-d-xo.htmlsi=KBy4S5mymP-_xwPa 3) Hamming Code: Error Correcting Code th-cam.com/video/t4kiy4Dsx5Y/w-d-xo.htmlsi=Jm-Mvz5ZoBmGQS05 4) SRAM vs DRAM th-cam.com/video/r787m_IaR1I/w-d-xo.htmlsi=flXSh3EmNu1ko6-i 5) Types of DRAM th-cam.com/video/DLM20pWqMyU/w-d-xo.htmlsi=z4jZUPkQsMZCDV9Q 6) Cache Memory: th-cam.com/video/Zr8WKIOIKsk/w-d-xo.htmlsi=8HBGfJL5Ye4WEGw_ 7) Semiconductor Memories: RAM th-cam.com/video/a--rNdqtwCI/w-d-xo.html
Please make a video on column multiplexing for memory and how many muxs are required while folding the whole memory cell , i mean that how the aspect ratio can be reduced in memory cell.
Sir, what is the difference between the logic circuit of 1 binary cell and using SRAM Cell (7:58)? At 14:43 it should be "k+1 inputs for each AND gate" Thank you for these amazing videos.
The SRAM cell circuit is the actual circuit. That is how the 1 bit of information is stored in the SRAM. But here the circuit which I have shown for 1 binary cell is a logical circuit. That is a way of representing the same circuit in a logical way.
In coincident decoding, the decoding logic is divided into row and column decoder. Here, for both row and column decoding when we use same address lines using time multiplexing( rather than separate address lines) then that is called address multiplexing. I hope, it will clear your doubt.
The link for the other useful videos related to memory and memory decoding:
1) Decoder Explained:
th-cam.com/video/a3wh7xV5PBU/w-d-xo.htmlsi=EXXa757x8mijj5Fz
2) Error Detecting Code: Parity Bit
th-cam.com/video/Bwih7_AT1oI/w-d-xo.htmlsi=KBy4S5mymP-_xwPa
3) Hamming Code: Error Correcting Code
th-cam.com/video/t4kiy4Dsx5Y/w-d-xo.htmlsi=Jm-Mvz5ZoBmGQS05
4) SRAM vs DRAM
th-cam.com/video/r787m_IaR1I/w-d-xo.htmlsi=flXSh3EmNu1ko6-i
5) Types of DRAM
th-cam.com/video/DLM20pWqMyU/w-d-xo.htmlsi=z4jZUPkQsMZCDV9Q
6) Cache Memory:
th-cam.com/video/Zr8WKIOIKsk/w-d-xo.htmlsi=8HBGfJL5Ye4WEGw_
7) Semiconductor Memories: RAM
th-cam.com/video/a--rNdqtwCI/w-d-xo.html
Please make a video on column multiplexing for memory and how many muxs are required while folding the whole memory cell , i mean that how the aspect ratio can be reduced in memory cell.
Tough topics become sooo easy with your excellent technique of making video lectures 🎉👏🏻👏🏻
Excellent, its very clear.
Sir, what is the difference between the logic circuit of 1 binary cell and using SRAM Cell (7:58)?
At 14:43 it should be "k+1 inputs for each AND gate"
Thank you for these amazing videos.
The SRAM cell circuit is the actual circuit. That is how the 1 bit of information is stored in the SRAM. But here the circuit which I have shown for 1 binary cell is a logical circuit. That is a way of representing the same circuit in a logical way.
eğer bugün konuları bitirirsem you are my new crush.......
What is the difference between address multiplexing and coincident circuits ? 18:38
In coincident decoding, the decoding logic is divided into row and column decoder. Here, for both row and column decoding when we use same address lines using time multiplexing( rather than separate address lines) then that is called address multiplexing. I hope, it will clear your doubt.
Very very nice 🎉🎉
can we use a tri state gate for select line cuz output will be 0 when s = 0 but if s = 1 output can actually be 0 i.e. stored data can be 0
We need video about comm protocal LIKE UART SPI I2C Can Lin
how to cascade such 1 bit ram modules to obtain 2 x 8 ram memory module??
In the video, I have already shown how to design 16*4 RAM using 1 bit RAM module. If you watch the entire video you will get it.
You're amazing... Love fom Bangladesh
Assembly language 8086
MPRS 686520
❤ AUG 2024❤
Please also provide the source of this information.
digital design by Morris Mano
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You may use subtitles.
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