There is a mistake in MOSFET based totem pole circuit. The P channel is supposed to be upside down. Please go through reference documents for accurate circuit.
Good video... But one issue is that, while replacing with complimentary MOSFET irrespective of gate supply for the totem circuit the upper MOSFET will be conducted through its parasitic diode...
Actually the gate of the power fet should have back to back zener diodes apx. 18 volts. As a MOSFET the Miller effect will show large transients at the gate when driving large currents, these can damage the drive circuitry.
For BJT totem pole Vcc is correct name of supply voltage,c-collector.Vdd for mosfets.For correct work of mosfet totem pole RD circuit in gate supply needed for different rise/fall times to prevent shoot through
Oh No!!! There is big mistake in my video. The P channel is supposed to be upside down. I am blurring the MOSFET part for the future references. Thank you so much for highlighting this mistake!!
What the problem is to take a 50-150MHz medium power BJT? I didn't get your statement that BJT TPD is slow. Use a cascode to mitigate Miller's effect if you wish
This information was taken almost verbatim from Texas Instruments application note SLUA618A, section 10: Bipolar Totem-Pole MOSFET Driver. Edit: I see now that you reference this in your description, making my point moot.
Are Vdd and Vbias the same value？The smoothing transistor between the two bypass capacitor might conduct some current if Vdd and Vbias are not the same, am I right?
What is shown is not a totem pole. A totem pole is based on transistors of the same type of conductivity. It is a very bad usage of a complimentary power amplifier.
Thanks for the teaching. one more sir what can be the reason of overheating on mosfet even when it been operated with totten pole to drive the mosfet on smps ur help sir. again I want to know how I can add 12v in gate drive transformer please I need the transformer coiling circuit diagram thanks
That depends on many factors. Namely the T-on and T-off switching times of the bjt or mosfet. For bipolar transistors the amount of current required to drive the transistors fully into saturation and turn them fully on or off is critical as well. For mosfets the gate charge plays a critical role (Qg). Enough current to fully charge the gate to get the mosfet is very important. The amount of current required for the mosfet gate to charge is determined by the gate charge (Qg) divided by the turn on time (T on).
I use this today’s and the 15 voltage to the totem pole blow my gate on mosfet I did this same design and it keeps blowing my mosfet hat I don’t understand why my data sheet said only 5 volt to gate so should I use only 5 volt to driver
Go get a electrical engineering degree or you can just take a circuits class and electronics 1 class (with appropriate math backgrounds) and you will be able to understand any schematic
Has anyone figure out yet how circulation pump motor works? I know it uses gate driver in IC to drive gates in IGBT. It is 3 phase too. pump name Wilo made in sweden or something. Same shit is in those compressor heater/cooler, the fans are run by PMM thats driven by weird pwm using gate drivers and IGBT. I wan to make them run on 12 or 24v DC. Any smart person here? I could even pay if you know where to tap the pcb.
@@nikolaivic4480 well, while the gate voltage won't under any circumstances exceed vbias - 0.6v, it'll definitely help to keep the mos OFF. If you wanna make the mos gate reach vdd (or higher), you might wanna change the driving system (or going for bootstrap caps respectively). This drivers are good for logic gate MOSFETs, hence the need to keep the gate always low. Edit: if that resistor is large enough (given Q1's hfe, you may even put that BJT in deep-saturation, hence reaching VDD - 0.3V, but again, not VDD.
@@codures Vbias is 3v3 or 5v if it is a uC. VDD should be 10V for normal level FET to reach lowest Rdson. Emitter follower is not a good solution in that case, maybe for logic level FETs. Common emitter topology is better.
All that is is a push-pull driver for a MOSFET which is basic common knowledge dating back to the 1950's & earlier in valve audio amps the only difference is there's no biasing between the bases as its logic!
@@jimedgar6789 Fun that I wasn't alive till the mid 60's but it still common knowledge & I'm not a hater or a DUDE!... I'm a bloke with vast electronics knowledge!
@@preston963 I dig it. But still nice to be taught the old stuff. Not every knows it. Like Ohm's law. when you get it, you really understand more than you ever did. I am learning new stuff every day and have been doing this for three decades :)
Pnp bjts and PMOS transistors are both conduct current when you apply 0 volts to the base/ gate. This is opposite of npn or NMOS trasistors that only conduct current when succificent voltage is applied at base/gate
You are correct. However, it works when the gate of the next FET circuit is charged up close to VDD. It looks like the pnp Q2 when turned on with its emitter at near VDD, it would be in Saturation condition, then goes into Active as VDD drops, then turing OFF as VDD approaching 0 + VBEon. Similarly for top npn Q1. So iniitally when the controller send out a 0v low and the output is at 0v, Q1 does not work and the circuit does nothing. However, when the controller output goes H, Q1 would work and charge the output to VDD - VCEsat. And it works from there on. Some initial voltage at the output of the totem pole circuit in between could cause the initial half of the PWM L or H from the controller not to work intiialy, but the next half of the PWM of the opposite value would work and charge or discharge the output to the operating levels the BJTs citcuit needs - as explained above. Is this correct, the author ?
The PMOS in the circuit is upside down, and when corrected, its body is connected to VDD. When PWM output is say 0V at the gate of the PMOS, a channel is formed under the SiO2 of the gate and the PMOS is on. Similarly for the NMOS below, the body is connected to GND 0V, when you put in something above the VGS threshold, VDD or not neccesarily VDD but just above VGS threshold, then similarly to the PMOS above, a channel is formed an the NMOS turned on and discharge the output of the CMOS circuit. If for experiment, if you can connect NMOS body to VDD by reverse the D-S, it will not work when PWM is VDD but will turn on when PWM is 0v which both PMOS and NMOS are on. BJT on and off conditions are different as explained in the other reply here.
For th elast sentence of the long 2nd paragraph, the other problem when connected the MOSFET in reverse is that it will be on in the reverse logic due to the body diodes are reverse.
There is a mistake in MOSFET based totem pole circuit. The P channel is supposed to be upside down. Please go through reference documents for accurate circuit.
also mosfet totem pole need RD circuit in gate for different Ton & Toff times.else driver will produce a lot of heat
Good video... But one issue is that, while replacing with complimentary MOSFET irrespective of gate supply for the totem circuit the upper MOSFET will be conducted through its parasitic diode...
Actually the gate of the power fet should have back to back zener diodes apx. 18 volts. As a MOSFET the Miller effect will show large transients at the gate when driving large currents, these can damage the drive circuitry.
For BJT totem pole Vcc is correct name of supply voltage,c-collector.Vdd for mosfets.For correct work of mosfet totem pole RD circuit in gate supply needed for different rise/fall times to prevent shoot through
6:40 The drain and source of Q1 are reversed. The body diode makes a big short circuit.
Sorry for that! please check description
Great video. This type of videos is very useful for me.
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There Is some problem with the High side mosfet, the internal diode as shown in the schematics Will conduct Always to the gate of the Power mosfet
Oh No!!! There is big mistake in my video. The P channel is supposed to be upside down. I am blurring the MOSFET part for the future references. Thank you so much for highlighting this mistake!!
Thanks from Brazil, great video.
You'll notice in the push pull stage that you need a PNP and an NPN transistor, whereas the totem pole driver uses only NPN transistors
Great video! 😀
Thank you so much for watching!! Please don't forget to subscribe to our channel
Made total sense to me. Well explained sir.
.perfeito, obrigado e parabens.
Highside mosfet of totempole has body diode in downward direction it means even if the mosfet is off the diode conducts
What the problem is to take a 50-150MHz medium power BJT? I didn't get your statement that BJT TPD is slow. Use a cascode to mitigate Miller's effect if you wish
Excellent instruction once again.
Thank you so much for watching!! Please don't forget to subscribe to our channel
Sir well done for your job you have done so far. Could please make a video about smps control loop stability and emphasizr on rhpz please
will work on it, please don't call me sir!
Great video! Thank you.
Would vdd not be lower than 10v due to the diodes forward voltage drop?
What are the best bjt for totem pole to switch gate faster with good current
This information was taken almost verbatim from Texas Instruments application note SLUA618A, section 10: Bipolar Totem-Pole MOSFET Driver.
Edit: I see now that you reference this in your description, making my point moot.
Are Vdd and Vbias the same value？The smoothing transistor between the two bypass capacitor might conduct some current if Vdd and Vbias are not the same, am I right?
Should they be igbt? Good video.
What is shown is not a totem pole. A totem pole is based on transistors of the same type of conductivity. It is a very bad usage of a complimentary power amplifier.
Could you just replace the totem pole with a single BJT NPN? What is the benefit of having the totem pole (made up of BJT) over a single BJT?
Thanks for the teaching. one more sir what can be the reason of overheating on mosfet even when it been operated with totten pole to drive the mosfet on smps ur help sir. again I want to know how I can add 12v in gate drive transformer please I need the transformer coiling circuit diagram thanks
Does a totem pole provide for a higher rise & fall time of the gate pulse? Or is it only the fall time that would be quicker? Thank you, Benjamin.
both will be quicker
Very good master
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❤❤❤Sir q2 transistor change input diod no working
I think inductor on far right is toroid with ferrite core, isn't it.
what is the switching frequency limit fo this circuit if bjt is used?
That depends on many factors. Namely the T-on and T-off switching times of the bjt or mosfet. For bipolar transistors the amount of current required to drive the transistors fully into saturation and turn them fully on or off is critical as well. For mosfets the gate charge plays a critical role (Qg). Enough current to fully charge the gate to get the mosfet is very important. The amount of current required for the mosfet gate to charge is determined by the gate charge (Qg) divided by the turn on time (T on).
Very helpful ☺️🙏
Thank you so much for watching!! Please don't forget to subscribe to our channel
How can you avoid the HIGH current flowing in Q1/Q2 when transitioning?
Thank you very much, can I use it in ic555 output?
yes you can use the 555
How can we make the gate pin negative 9 volts while the MOSFET stops conducting electricity? Help me make a video thank you.
You can use a voltage divider circuit. For eg. total supply is 24V, you can add two resistors (and Zener diodes) to get 18V and -8V.
I use this today’s and the 15 voltage to the totem pole blow my gate on mosfet I did this same design and it keeps blowing my mosfet hat I don’t understand why my data sheet said only 5 volt to gate so should I use only 5 volt to driver
Yes, please use only 5V if the datasheet mentions the same
Using a gate resistor?
Need a 5V zener on the gate to ground to clamp the voltage
Wouldn't using mosfets as todem defeat the protection of the bjts?
yes you can but again it will be a complicated and not cost effective
very2 excellent
Great, but why's it called a Totem pole?
Hi, I'm novice in electrnics pls can you help to understand how to read schematic.
Go get a electrical engineering degree or you can just take a circuits class and electronics 1 class (with appropriate math backgrounds) and you will be able to understand any schematic
Could u pls tell why Q1 is required
I think Q1 is there to provide enough charge to the MOSFET gate for turning it on fast
@@long-d4kYes, thank you
Has anyone figure out yet how circulation pump motor works? I know it uses gate driver in IC to drive gates in IGBT. It is 3 phase too. pump name Wilo made in sweden or something. Same shit is in those compressor heater/cooler, the fans are run by PMM thats driven by weird pwm using gate drivers and IGBT. I wan to make them run on 12 or 24v DC.
Any smart person here? I could even pay if you know where to tap the pcb.
Sir can you please do it on practical so that we can make it and take it on real life
I don't have lab setup as of now to do the hands on! will surely work in future
What if VDD>Vbias is required?
Well, you add a parallel resistor to Q2 (the Emitter-Collector section).
@@codures How is that gonna charge the gate to VDD and not to Vbias only?
@@nikolaivic4480 well, while the gate voltage won't under any circumstances exceed vbias - 0.6v, it'll definitely help to keep the mos OFF.
If you wanna make the mos gate reach vdd (or higher), you might wanna change the driving system (or going for bootstrap caps respectively). This drivers are good for logic gate MOSFETs, hence the need to keep the gate always low.
Edit: if that resistor is large enough (given Q1's hfe, you may even put that BJT in deep-saturation, hence reaching VDD - 0.3V, but again, not VDD.
@@codures Vbias is 3v3 or 5v if it is a uC. VDD should be 10V for normal level FET to reach lowest Rdson. Emitter follower is not a good solution in that case, maybe for logic level FETs. Common emitter topology is better.
@@nikolaivic4480 totem hater, lol.
👌
Please remake the video with accurate circuit
All that is is a push-pull driver for a MOSFET which is basic common knowledge dating back to the 1950's & earlier in valve audio amps the only difference is there's no biasing between the bases as its logic!
Dude, I was not alive in the 50s. So good knowledge, well presented.
Don't be a hater, boomer.
@@jimedgar6789 Fun that I wasn't alive till the mid 60's but it still common knowledge & I'm not a hater or a DUDE!... I'm a bloke with vast electronics knowledge!
@@preston963 I dig it. But still nice to be taught the old stuff. Not every knows it. Like Ohm's law. when you get it, you really understand more than you ever did. I am learning new stuff every day and have been doing this for three decades :)
Sub titles is bloody hell.
Please work on your english.
Video is fantastic though.
okay
there is nothing wrong with his english
His English is way better than your attitude.
Draaaaaaaaaag
Haha wtf
Pwm doesn’t have minus low pulses only high and zero
so how it can open pnp bjt?
Pnp bjts and PMOS transistors are both conduct current when you apply 0 volts to the base/ gate. This is opposite of npn or NMOS trasistors that only conduct current when succificent voltage is applied at base/gate
You are correct. However, it works when the gate of the next FET circuit is charged up close to VDD. It looks like the pnp Q2 when turned on with its emitter at near VDD, it would be in Saturation condition, then goes into Active as VDD drops, then turing OFF as VDD approaching 0 + VBEon. Similarly for top npn Q1.
So iniitally when the controller send out a 0v low and the output is at 0v, Q1 does not work and the circuit does nothing. However, when the controller output goes H, Q1 would work and charge the output to VDD - VCEsat. And it works from there on.
Some initial voltage at the output of the totem pole circuit in between could cause the initial half of the PWM L or H from the controller not to work intiialy, but the next half of the PWM of the opposite value would work and charge or discharge the output to the operating levels the BJTs citcuit needs - as explained above.
Is this correct, the author ?
The PMOS in the circuit is upside down, and when corrected, its body is connected to VDD. When PWM output is say 0V at the gate of the PMOS, a channel is formed under the SiO2 of the gate and the PMOS is on.
Similarly for the NMOS below, the body is connected to GND 0V, when you put in something above the VGS threshold, VDD or not neccesarily VDD but just above VGS threshold, then similarly to the PMOS above, a channel is formed an the NMOS turned on and discharge the output of the CMOS circuit. If for experiment, if you can connect NMOS body to VDD by reverse the D-S, it will not work when PWM is VDD but will turn on when PWM is 0v which both PMOS and NMOS are on.
BJT on and off conditions are different as explained in the other reply here.
For th elast sentence of the long 2nd paragraph, the other problem when connected the MOSFET in reverse is that it will be on in the reverse logic due to the body diodes are reverse.
Squish-skwosh.
Excellent instruction once again.
Thank you! Cheers!