Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty

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  • เผยแพร่เมื่อ 6 ม.ค. 2025

ความคิดเห็น • 35

  • @kankanalasamhithachowdary236
    @kankanalasamhithachowdary236 3 ปีที่แล้ว +1

    We add skew in setup uncertainty only right( given formula), then why we added seperately at 13:15

    • @TeamVLSI
      @TeamVLSI  3 ปีที่แล้ว

      Hi Kankanala,
      We consider the skew in uncertainty only in preCTS stage. Once the clock tree is build, we have actually skew so we dont consider the skew in uncertainty.
      Watch again at @11:27, it will be clear.

  • @dn2358
    @dn2358 4 ปีที่แล้ว +2

    Keep uploading sir👍🙏

    • @TeamVLSI
      @TeamVLSI  4 ปีที่แล้ว +2

      Sure 👍, keep supporting...

  • @yuxiang026
    @yuxiang026 4 ปีที่แล้ว +3

    Thanks, a really good video. And it will be better If here are subtitles

    • @TeamVLSI
      @TeamVLSI  4 ปีที่แล้ว

      Thanks Yuxiang,
      It is my pleasure that you loved the video. I will try to add subtitle.

  • @niteeshfunworld4656
    @niteeshfunworld4656 3 ปีที่แล้ว +1

    Nice video and explanation

    • @TeamVLSI
      @TeamVLSI  3 ปีที่แล้ว

      Thanks a lot Niteesh. Stay tune and keep learning.

  • @komarashiva2091
    @komarashiva2091 5 หลายเดือนก่อน

    Sir in pre-cts u mentioned latency is negligible then how u calculate the skew(capture latency - launch latency)

  • @KomalsCreations_
    @KomalsCreations_ 4 ปีที่แล้ว +1

    Thanks for explanation

    • @TeamVLSI
      @TeamVLSI  4 ปีที่แล้ว

      Always welcome Komal,
      Keep watching, Keep supporting...

  • @nghiahiepbuiphuoc8946
    @nghiahiepbuiphuoc8946 4 ปีที่แล้ว +4

    It is a great video!!! I think the accuracy check (such as Min pulse width check, Min period check, clock as data check, ... ) is an interesting topic. Could you consider my suggestion?

    • @TeamVLSI
      @TeamVLSI  4 ปีที่แล้ว

      Thanks for the tips!

  • @joshnareddy7480
    @joshnareddy7480 9 หลายเดือนก่อน

    Can you please do video on clock gating and asynchronous checks in vlsi

  • @SUDIPTODUTTAGUPTA
    @SUDIPTODUTTAGUPTA 2 ปีที่แล้ว +1

    Thank you, sir. I have the following query: If the jitter source is from the common CLK, why do we need to consider it in Setup uncertainly? Shouldn't the jittered clocks (FF1/CK, FF2/CK) edges be moving in the same direction?

    • @TeamVLSI
      @TeamVLSI  2 ปีที่แล้ว +1

      Hi Sudipto,
      Yes, right. But in setup analysis launch and capture clock edges are different, and jitter is associate with edge.

    • @SUDIPTODUTTAGUPTA
      @SUDIPTODUTTAGUPTA 2 ปีที่แล้ว

      @@TeamVLSI Yes sir, I missed that part. Thanks for the explanation.

  • @vamsikrishnagedela8990
    @vamsikrishnagedela8990 ปีที่แล้ว +1

    hi sir, at time stamp 13.58 we are using uncernity (skew +margin+jitter) then why another skew componet ...is this calculation in post cts

    • @joshnareddy7480
      @joshnareddy7480 9 หลายเดือนก่อน

      Uncertainty will relax after CTS has built and we will keep uncertainty for synthesis to meet setup timing

  • @janapadakannadasongs
    @janapadakannadasongs 2 ปีที่แล้ว +1

    how to define the uncertainty value in sdc?

    • @TeamVLSI
      @TeamVLSI  2 ปีที่แล้ว

      Hi VP,
      Watch the full video, although at time 12:30 , it is explained.

  • @merrygo7189
    @merrygo7189 3 ปีที่แล้ว +1

    Why uncertainty is High in Half cycle paths?

  • @nanoelectronicsdemystified
    @nanoelectronicsdemystified 2 ปีที่แล้ว +1

    why are we considering setup/hold margin in uncertainty while we are also considering it for setup/hold calculation? (The margin in uncertainly refers to something else I think)

    • @TeamVLSI
      @TeamVLSI  2 ปีที่แล้ว

      I would love to see other name, If you have details Please share.

  • @arunpandiyananbarasu1455
    @arunpandiyananbarasu1455 4 ปีที่แล้ว +1

    Nice sir

    • @TeamVLSI
      @TeamVLSI  4 ปีที่แล้ว

      Thanks Arun. keep supporting...

  • @anithasabhavat6064
    @anithasabhavat6064 3 ปีที่แล้ว +1

    Hello sir,
    Who will set this uncertainty value?
    Synthesis ppl?

  • @shrikanthramanagara2382
    @shrikanthramanagara2382 2 ปีที่แล้ว +1

    THNK U

    • @TeamVLSI
      @TeamVLSI  2 ปีที่แล้ว

      Welcome 😊

  • @akashwayal8797
    @akashwayal8797 3 ปีที่แล้ว +1

    sir what is setup and hold margins? why are they required?

    • @TeamVLSI
      @TeamVLSI  3 ปีที่แล้ว +2

      Hi Akash,
      Positive slack is called the margin.
      In a particular data path if you want to fix setup, means you are going to reduce the delay of that data path, It may violate your hold. so you must have hold margin on that path and vice-versa.

    • @akashwayal8797
      @akashwayal8797 3 ปีที่แล้ว +1

      @@TeamVLSI Yes thank you !

  • @vikaspatel656
    @vikaspatel656 3 ปีที่แล้ว

    in RAT calculation you have taken time period in setup analysis but you have not taken time period in the hold analysis . why ???

    • @TeamVLSI
      @TeamVLSI  3 ปีที่แล้ว +1

      Hi Vikas,
      The answer is simple, We check hold on the same edge not on the next edge like setup.