Memory is always word addressable so Main memory becomes 4GB/32 i.e. 2^(32-5) bits i.e. 2^ 27 bits so main memory is 27 bits(2^27)Words Now, Block size is 8 words i.e. 2^3 words i.e. Block offset becomes 3.. (Block offset is same as word offset) Cache Size = 16KB i.e. 16KB/32 WORDS i.e. 2^14/2^5 i.e. 2^9 WORDS Now no of lines = Cache Size/Block Size = (2^9)/(2^3) = 2^6 no of sets = no of lines/4 as it is 4 way set associative so no of sets = (2^6)/4 i.e. 2^4 set no bits = 4 Now MAIN MEMORY bits = TAG bits + Set no BITS + Block offset It means 27 = x + 4 + 3 here x comes out to be 20 hence no of tag bits required is 20 Thanks (Knowledge Courtesy: RavindraBabuRavula Purchased Course)
As per me, the main memory is not always word addressable. Default is that we measure it in bits. We take it to be word addressable only when it is given in question...
I think you are confusing this question with direct mapping. You may also refer the portion marked as word as offset. Further since the question states that the memory is bit addressable, it will only be no. Of bits and not blocks. Also , the answers of all the questions posted in the channel are verified from a good source.
bro word bit is 8 and total physical address is 35 bit. here there are 8 words but each word contains 32 bits of memeory . we need to address each bit of memory . hence the word bit is 8
@@udaysaiphanindra3138 Memory is always word addressable. The word can be 8 bits or 16 bits or any number of bits. If a word is given then you need to have a unique address for that word. However the bits within the word will have same address. The very existence of the "word" concept in Computer Science is to say that the group of bits (word) together have the same address.
Hari Sadu, you're correct. The solution is wrong. The word size has nothing to do with the no. of words per block. The "word" field size is ALWAYS log2(no. Of words per block). It is clearly mentioned in the question that the no. of words per block is 8. Also bits are irrelevant for the simple reason that, main memory or cache memory addresses aren't bit addressable but word addressable. That's the definition of WORD.
The correct version is :-- Total Size of Address Field -- 30 bits (As the Physical Memory contains 2^32 bytes = 2^30 words (in this case)). Size of Word Field -- 3 bits (As each block contains 2^3 words) The rest is done similarly as expected.
maam word size is 2^2 bytes and then we multiply it with 2^3 blocks and from this we can find the word size by multiplying 2^2*2^3 = 2^5 and hence we get word as 5 bits
mam ,here we need to convert the total main memory into bits then we will need 35 bits to address. and the word bit will be 8 beacuse there are 8 words which needs 3 bits and each word contains 32 bits that require 5 bits thence total length of word bit is 8 and main memory is 35 bit set bit is 7 asual. and tag bit is 20.
>>>"W"--num of bits to identify a word >>>"T"--tag bits >>>"S"--set bits, to identify diff sets >>>cache capacity = 16KB = 2^14B {{{{{{{{{ >>>1 block contains 8 words so "W" = log2(8)=3 }}}}}}}} block of 8 words, each word of 32 bits >> total block size 8*32=256bits=2^8bits= 2^5B >>>so, No. cache blocks =2^14/2^5=2^9 >>>as it is 4 way so No. of cache sets 2^9/2^2=2^7 >>>bits req to identify all cache sets "S"=log2(2^7)=7 {{{{{{ >>>main memory---->4GB-->2^32B so number of words in MM=size of MM/each Word size(32bit--4B)=2^32/4=2^30 >>>bits req to identify each words=log2(2^30)=30 }}}}}}}>so tag bits "T" =30-7-3=20 >>>"T"S"W"-->20 7 3 >>>your ans is correct, but there is 2 mistakes mam
I think word length is independent of no of words in a block. If we have only 8 words in a block, then how can we place ( 2^5) words in a block. Because u have put word as 5 bit in address bit.. And also you have not converted byte to bit in physical address space .
Correction for the 2^5 thing: the portion represented as word (or offset in some books) represents the bits reqd to form all combinations of locations present in a block. So, it will be equal to bits reqd to represent the block size = (8 * 32)/8=2^5 -> 5 bits
@@ritukapurclasses1591Dear Mam you said the size of PA is 4GB or 2^32B and then you said we require 32 bits but mam don't we have to convert 2^32B to bits and then calculate the number of bits please clear this doubt as you did for the word length
For the number of blocks you converted the bytes to bits..but in case of the 4GB physical space..you didn't do it? Shouldn't it be (2^32)*(2^3) for converting it?
Ma'am , can u solve this ,i tried to solve it getting the answer 19 bits i think its wrong.... please solve this . An 8-way set associative cache memory unit with a capacity of 64 KB is built using a block size of 32 words. The word length is 32 bits. The size of the physical address space is 4 GB. Find the number of bits for the TAG field.
Can you please solve this question.. Write a program using 8086 assembly Language (with proper comments) that accepts a single character input from the keyboard, if this character is '+' then the program adds two six byte arrays stored in the memory into a third array in the memory, otherwise program simply terminates. Make suitable assumptions, if any. (The effect of addition should be similar to the array operation like: for i=1 to 6 {C[i]=A[i]+B[i];} )
can you please solve this question.. A computer has 4 GB RAM with each memory word of 64 bits. It has cache memory having 1024 blocks having a size of 128 bits (2 memory words). Show how the main memory address (C1AAF0AB)h will be mapped to cache address, if (i) Direct cache mapping is used (ii) Associative cache mapping is used (iii)Two way set associative cache mapping is used. You should show the size of tag, index, main memory block address and offset in your answer.
Cache has 1024 blocks => 2^10 blocks. Also, block size is given as 128 bits = 128/8 Bytes = 16 Bytes. Now, Main Memory (MM) or RAM size = 4 * (1024) MBs = 4* (1024)* (1024) KBs = 4* (1024)* (1024)* (1024) Bytes = 2^(32) => 32 bytes required to represent the MM address space. Since there are 1024 blocks in cache, and 1024 = 2^10 => 10 bytes required to index blocks in cache. Since block size if 128 = 2^7 => 7 bytes to index words in a block. So, for i) Direct cache mapping-> Tag bits = 32-(10 + 7) = 15. So,tag - index - offset become 15 - 10 - 7, and to map C1AAF0AB, we would split it as C1A-101-0-F0-1-010-B: Tag=C1A101, index=0F01, offset=010B, which when converted from hex to 40bit binary notation would be: Tag=1100 0001 1010 101, index=0 1111 0000 1, and offset=010 1011. For associative mapping, we have only tag and offset, with offset bit as 7 and tag = 15+10=25 -> for mapping the given word, Split would be C1AAF0-1-010-B=> Tag=1100 0001 1010 1010 1111 0000 1 and offset= 010 1011. Lastly for 2-way Set-Associative => 2 blocks per set, we compute the number of sets as No. of blocks in cache/2 = 1024/2 = 512 = 2^8 => 8 bytes to address different sets => Tag bits = 32-8-7 = 17. So, Tag-Set-Offset becomes 17-8-7. So, to to map C1AAF0AB, split is C1AA-1-111-0-1-010-B. So, TAG=1100 0001 1010 1010 1, SET=111 0 1, and OFFSET= 010 1011. You could get better clarity by going through solved examples in this playlist.
Hi mam , I have doubt on similar types of question like Consider a cache memory of 16 words. Each block consist of 4 words. Size of the main memory is 256 bytes . Draw associative mapping and calculate TAG and word size So please can you give solution please
You got the right answer but your approach is wrong..it's given word length is 32 bits that is indicating word addressable..it doesn't mean word field contains 5 bits..if it had been given there are 32 words in a block than you can write 2^5 and with 5 bits u can identify each word. World length and no of words are two different things
Hi mam ....plz provide ur email id(if u r comfortable to share) ...i want to send u the pic of solution that i solve by assuming word addressable memory still tag bits are 20 only but difference will be in approach...so for written exam i want to know which is the correct method your or mine...thanku
SORRY to say mam . you teach very good . but you teach wrong . first of all cache do not have blocks , it have lines. due to your teaching I made mistake in exam. after exam I got to know that cache has line . pleaer atleast clear your concepts while teching others.
Blocks is used as a synonym for lines in many Gate questions and textbooks... you'll get to know about it as you start practicing Gate questions... All d best...
Memory is always word addressable
so Main memory becomes 4GB/32 i.e. 2^(32-5) bits i.e. 2^ 27 bits
so main memory is 27 bits(2^27)Words
Now, Block size is 8 words i.e. 2^3 words i.e. Block offset becomes 3.. (Block offset is same as word offset)
Cache Size = 16KB i.e. 16KB/32 WORDS i.e. 2^14/2^5 i.e. 2^9 WORDS
Now no of lines = Cache Size/Block Size = (2^9)/(2^3) = 2^6
no of sets = no of lines/4 as it is 4 way set associative
so no of sets = (2^6)/4 i.e. 2^4
set no bits = 4
Now MAIN MEMORY bits = TAG bits + Set no BITS + Block offset
It means
27 = x + 4 + 3
here x comes out to be 20
hence no of tag bits required is 20
Thanks
(Knowledge Courtesy: RavindraBabuRavula Purchased Course)
As per me, the main memory is not always word addressable. Default is that we measure it in bits. We take it to be word addressable only when it is given in question...
@@ritukapurclasses1591 the block size is 8 words.so only 3 bits required for word offset within block. You should not convert word to bits.
Your solution is wrong. The word field is 3 not 5. It is used to represent " The number of words a block has" not "the number of bits in the word".
I think you are confusing this question with direct mapping. You may also refer the portion marked as word as offset. Further since the question states that the memory is bit addressable, it will only be no. Of bits and not blocks. Also , the answers of all the questions posted in the channel are verified from a good source.
bro word bit is 8 and total physical address is 35 bit. here there are 8 words but each word contains 32 bits of memeory . we need to address each bit of memory . hence the word bit is 8
@@udaysaiphanindra3138 Memory is always word addressable. The word can be 8 bits or 16 bits or any number of bits. If a word is given then you need to have a unique address for that word. However the bits within the word will have same address. The very existence of the "word" concept in Computer Science is to say that the group of bits (word) together have the same address.
Hari Sadu, you're correct. The solution is wrong. The word size has nothing to do with the no. of words per block. The "word" field size is ALWAYS log2(no. Of words per block). It is clearly mentioned in the question that the no. of words per block is 8. Also bits are irrelevant for the simple reason that, main memory or cache memory addresses aren't bit addressable but word addressable. That's the definition of WORD.
The correct version is :--
Total Size of Address Field -- 30 bits (As the Physical Memory contains 2^32 bytes = 2^30 words (in this case)).
Size of Word Field -- 3 bits (As each block contains 2^3 words)
The rest is done similarly as expected.
maam word size is 2^2 bytes and then we multiply it with 2^3 blocks and from this we can find the word size by multiplying 2^2*2^3 = 2^5 and hence we get word as 5 bits
Such a beautiful handwriting 😲😲never seen in any teacher
These are really amazing videos... would be happy to get some more examples
mam ,here we need to convert the total main memory into bits then we will need 35 bits to address. and the word bit will be 8 beacuse there are 8 words which needs 3 bits and each word contains 32 bits that require 5 bits thence total length of word bit is 8 and main memory is 35 bit set bit is 7 asual. and tag bit is 20.
Thanks, a great help!
>>>"W"--num of bits to identify a word
>>>"T"--tag bits
>>>"S"--set bits, to identify diff sets
>>>cache capacity = 16KB = 2^14B
{{{{{{{{{ >>>1 block contains 8 words so "W" = log2(8)=3 }}}}}}}} block of 8 words, each word of 32 bits >> total block size 8*32=256bits=2^8bits= 2^5B
>>>so, No. cache blocks =2^14/2^5=2^9
>>>as it is 4 way so No. of cache sets 2^9/2^2=2^7
>>>bits req to identify all cache sets "S"=log2(2^7)=7
{{{{{{ >>>main memory---->4GB-->2^32B so number of words in MM=size of MM/each Word size(32bit--4B)=2^32/4=2^30
>>>bits req to identify each words=log2(2^30)=30 }}}}}}}>so tag bits "T" =30-7-3=20
>>>"T"S"W"-->20 7 3
>>>your ans is correct, but there is 2 mistakes mam
I think word length is independent of no of words in a block.
If we have only 8 words in a block, then how can we place ( 2^5) words in a block. Because u have put word as 5 bit in address bit..
And also you have not converted byte to bit in physical address space .
We do not always perform d byte to bit conversion. If the address is in bytes you do not do that.
Correction for the 2^5 thing: the portion represented as word (or offset in some books) represents the bits reqd to form all combinations of locations present in a block. So, it will be equal to bits reqd to represent the block size = (8 * 32)/8=2^5 -> 5 bits
@@ritukapurclasses1591Dear Mam you said the size of PA is 4GB or 2^32B and then you said we require 32 bits but mam don't we have to convert 2^32B to bits and then calculate the number of bits please clear this doubt as you did for the word length
For the number of blocks you converted the bytes to bits..but in case of the 4GB physical space..you didn't do it? Shouldn't it be (2^32)*(2^3) for converting it?
Same question?
Thanks for explaining .Now I'm more clear with this topic...
+Ajay Nagvanshi Glad to help you :)
thank you mam i like the way you teach
Thank you for the appreciation :)
Ma'am , can u solve this ,i tried to solve it getting the answer 19 bits i think its wrong.... please solve this .
An 8-way set associative cache memory unit with a capacity of 64 KB is built using a block size of 32 words. The word length is 32 bits. The size of the physical address space is 4 GB. Find the number of bits for the TAG field.
Can you please solve this question..
Write a program using 8086 assembly Language (with proper comments) that accepts a
single character input from the keyboard, if this character is '+' then the program adds two
six byte arrays stored in the memory into a third array in the memory, otherwise program
simply terminates. Make suitable assumptions, if any. (The effect of addition should be
similar to the array operation like:
for i=1 to 6 {C[i]=A[i]+B[i];} )
can you please solve this question..
A computer has 4 GB RAM with each memory word of 64 bits. It has cache memory having 1024 blocks having a size of 128 bits (2 memory words). Show how the main memory address (C1AAF0AB)h will be mapped to cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii)Two way set associative cache mapping is used.
You should show the size of tag, index, main memory block address and offset in your answer.
Cache has 1024 blocks => 2^10 blocks. Also, block size is given as 128 bits = 128/8 Bytes = 16 Bytes. Now, Main Memory (MM) or RAM size = 4 * (1024) MBs = 4* (1024)* (1024) KBs = 4* (1024)* (1024)* (1024) Bytes = 2^(32) => 32 bytes required to represent the MM address space. Since there are 1024 blocks in cache, and 1024 = 2^10 => 10 bytes required to index blocks in cache. Since block size if 128 = 2^7 => 7 bytes to index words in a block. So, for i) Direct cache mapping-> Tag bits = 32-(10 + 7) = 15. So,tag - index - offset become 15 - 10 - 7, and to map C1AAF0AB, we would split it as C1A-101-0-F0-1-010-B: Tag=C1A101, index=0F01, offset=010B, which when converted from hex to 40bit binary notation would be: Tag=1100 0001 1010 101, index=0 1111 0000 1, and offset=010 1011.
For associative mapping, we have only tag and offset, with offset bit as 7 and tag = 15+10=25 -> for mapping the given word, Split would be C1AAF0-1-010-B=> Tag=1100 0001 1010 1010 1111 0000 1 and offset= 010 1011.
Lastly for 2-way Set-Associative => 2 blocks per set, we compute the number of sets as No. of blocks in cache/2 = 1024/2 = 512 = 2^8 => 8 bytes to address different sets => Tag bits = 32-8-7 = 17. So, Tag-Set-Offset becomes 17-8-7. So, to to map C1AAF0AB, split is C1AA-1-111-0-1-010-B. So, TAG=1100 0001 1010 1010 1, SET=111 0 1, and OFFSET= 010 1011. You could get better clarity by going through solved examples in this playlist.
@@ritukapurclasses1591 thanku so much mam❤❤
Hi mam ,
I have doubt on similar types of question like
Consider a cache memory of 16 words. Each block consist of 4 words. Size of the main memory is 256 bytes . Draw associative mapping and calculate TAG and word size
So please can you give solution please
Amazing explanation
You got the right answer but your approach is wrong..it's given word length is 32 bits that is indicating word addressable..it doesn't mean word field contains 5 bits..if it had been given there are 32 words in a block than you can write 2^5 and with 5 bits u can identify each word. World length and no of words are two different things
man plz upload the hole syllabus of COA.. it's my humble request to you...
+SUDHANSHU KUMAR For Sure... I'll start uploading them from this weekend itself...
thank u mam
I have uploaded some and will be putting on some more this week...
Hello mam, do you post all videos required for GATE ??
Thank you for Explaining .
+Zeeshan Najeeb Always a Pleasure :)
can you make a video on CACHE SYNONYM
Is this some sort of joke?
why you convert blocks in bits??
Thanks ma'am, this question came in my mid sem
Oh great bro..hope it comes in my end semester 🙃🙃🙃 .I can get full/full😅😅
Great amazing explanation very clear...keep it up. Btw which pen do you use while explaning
Thank you... I use variety of permanent markers...
Nice voice
Thank you :)
solution is wrong
Hi mam ....plz provide ur email id(if u r comfortable to share) ...i want to send u the pic of solution that i solve by assuming word addressable memory still tag bits are 20 only but difference will be in approach...so for written exam i want to know which is the correct method your or mine...thanku
Sure... Its rkclasses15@gmail.com
Ritu Kapur Classes mail sent plz check and reply on mail...thanku mam
Yes I'm a bit busy but will get back to you soon...
SORRY to say mam . you teach very good . but you teach wrong . first of all cache do not have blocks , it have lines. due to your teaching I made mistake in exam. after exam I got to know that cache has line . pleaer atleast clear your concepts while teching others.
Blocks is used as a synonym for lines in many Gate questions and textbooks... you'll get to know about it as you start practicing Gate questions... All d best...
Your concepts are wrong