Power Electronics WK3_2 MOSFET Turn On Characteristics
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- เผยแพร่เมื่อ 30 ก.ค. 2024
- A look in the capacitances that limit the speed at which we can turn on and off a MOSFET. The Miller plateau is presented and discussed. A simple examples is provided.
You saved me a lot of time searching for the answers behind the operation characteristics of the mosfet. THANK YOU!!!! You sir, are amazing at teaching!
You are welcome. Best wishes on your designs. - Dr. K
Very good presentation of MIOSFET turn on characteristics. Really good that you show how charge control calculations are done in a design.
14:20 I'm glad you said AVERAGE current. I see so many people making the mistake of saying dQ/dt = PEAK current which is completely wrong. Since the gate is a capacitor resistor network, the peak current can be estimated by Q/t * 5 (five time constants).
Dr. K,
Thank you very much for your videos! I'm currently binge watching all of them. I'm glad that you decided to share your knowledge with us. Hopefully TH-cam will sooner or later start recommending your videos more often.
GZY, glad the videos help. These were prepared in part for a course that I teach at Milwaukee School of Engineering. We are a smaller private university in Milwaukee, WI. I believe that the latest trends in WBG devices along with low-cost embedded controllers is transformational for high-power, high-efficiency, and low cost. The next 10 years are going to be great to watch as SiC and GaN become mainstream. Thanks for watching. -Dr. K
This is exactly the video I needed! Thank you.
Been confused on this all night, this veideo helped a lot.
Glad it was helpful. Thank you for supporting the channel! -Dr. K
Amazing content as always! Thank you Dr. K.
Kamal, thank you. Best wishes on y our designs. -Dr. K
Thank you very much! You helped me out A LOT
Hello Dr.k,
Thanks for your sharing. I feel much clear on how to determine a peak value of gate current so that I could choose and design a proper driver network .
You are welcome. Glad the videos helped. -Dr. K
Thank you for your Video!
I'm a electrical engineering student from germany and our professor does not explain this very well. And by using the books he refers to, it takes way too much time to extract/understand the more basic function of this behavior. In this 18 minute Video I learned more than by dealing with all this alone for 2 hours, thank you so much!
You are welcome. Where in Germany? MSOE has a dual degree program with the THL in Luebeck and our German students are required to take this class in their 4th year. Also, lots of great work on power electronics, motors, motor control, and EV technology happening in German based companies. Best wishes on your design. -Dr. K
@@powerelectronicswithdr.k1017thank you. I live in Bavaria and I'm a student at TH Georg Simon Ohm Nuremberg, so no connecting to Lübeck. But that sounds like a pretty cool program.
We're having a big course "circuit technology" in 4th semester of my bachelor's degree right now, so this is where we learn about this power-mos behavior.
Excellent!!
Great learning experience, kudos👍
Thank you.
It was wonderful lecture
Thank you.
Very helpful explanation!
Glad it was helpful and thank you for watching.
For the resistive load case, if the current Id = gm(Vg - Vth), why does the current Id continue to rise, despite Vg being held constant at the miller voltage?
Simple and clear..
Thank you!!
I love your clip
excellent vid!
Yuchen, thanks! -Dr. K
Thanks máster
Groovy
Hi Dr. K, Wonderful explanation. I had a small doubt though...how do we calculate the switching time of the FET, is it the RC time constant ? In this case C=Cgs+Cgd and R=Rg....from your explanation I can see that when both capacitors are charged, the Vd finally drops and the FET is on...am I thinking it right?
nice explanation cuh
Dr.K, I have a basic question for you. You say during start of turn on current actually flows through Cgd. My question is why does this current flow occur? I mean since capacitor is sitting at a higher voltage and charged, should we have no current to it until it is discharged or less than VGS? Consequently, why doesn't Cgd discharge via gate driver resistor as soon as bias is applied? Thank you!
Thank you so much Sir. 🙏🙏🙏🙏
You are welcome. Best wishes on your designs. -Dr. K
Why the chart at 16:20 shows the drain current not falling together with rising drain voltage even though the load type considered in the discussion is resistive? Is this a mistake?
Hi Nishanth, you are correct that the falling drain current and rising voltage would happen at the same rates. This would be a graph for an inductive load with a flyback diode. Sorry for the confusion and great observation! Best wishes on your design. -Dr. K
@@powerelectronicswithdr.k1017 thanks for the content. It seems its quite rare to find material and charts on fet miller plateau in resistive load context.
A followup question, if Load resistor on drain is zero (such a circuit would be practically useless i guess. But just for understanding the mechanism), then the plateau wont appear at the gate any more, but drain current would rise to the max as per vgs and vds.. Would this expectation be correct?
1. I wonder why Cds could be ignored? It starts from VDD and discharges to 0.
2. What circuit model is that used in the circuit analysis? Large signal model? Which operating region?
Hi Trunke, Cds is part of Coss. Coss = Cds + Cgd and Ciss = Cgd + Cgs. We look at Ciss as it is the capacitance that our gate driver has to work with. The gate driver has to push and pull charge into and out of the gate of the devices. Realistically, Cds does impact the turn-off time (which is often shorter than the turn-on time). I know this might not be a good explanation. Here's another source to help www.vishay.com/docs/73217/an608a.pdf. Best wishes on your design. -Dr. K
@@powerelectronicswithdr.k1017 Thank you very very much professor! Since I'm new to power electronics, I've learned a lot through your videos! And thanks for sharing the supplementary material! 🙏
Hello Dr. K!
I came across your channel a while ago and the material is very good. Thank you for your videos. You are a good teacher.
I have a question about the consumption of MOSFETs.
If I am not wrong:
- The total consumption is equal to % of time in saturation multiplied by the power due to RDS(ON), added to the power due to the two switching (on / off) multiplied by the frequency.
(Proportional part of the time in saturation, plus two switchings, every period. The absolute power loss of ecah switch is independent of the frequency).
- All the power consumed by the MOSFET is transformed into heat.
If that is correct, measuring the temperature that the transistor reaches and dividing by the thermal resistance R-JC, we should have more or less the same number, is that correct?
I am doing tests with several MOSFETs to see it experimentally, and I see a very strange temperature graph: For a pwm of 10 KHz, pulses between 1% and 3% cause the temperature to rise excessively, and then it gradually drops to the calculated theoretical value. I've measured that temperature for 10, 20, 30 .... 250, and then 500, 750, 1000... 4095, with a 12 bits pwm. Lot of points.
For an IRF540, for example, the temperature reached with a duty of 2 us is 14ºC, and with 20 us it is 9ºC (above ambient temperature).
This is normal? Why can it happen?
If you find it strange and want me to send you specific information about the tests, I would be happy to do so.
(Sorry for my English, I'm Spanish, I hope you will understad that I wanted to explain...)
Thank you so much!
Sir ,rc sunbber curcite for power diode paller how to calculated resistance, capacitor value pl. Video sed
Hello brother and sister I like your video thank you
You are welcome. Hope this helped with your design. Thank you for watching.
Dear Dr. K, you have explained some equations and showed plot of VGS waveform. Here a flat Miller plateau is shown for VGS. I agree with it for low side NMOS power device. But how about high side NMOS power device? Do you expect Miller region in VGS waveform for high side NMOS device during switching?
According to my understanding high side NMOS device will act as source follower (voltage gain ~1). It’s drain is connected to fixed supply voltage so CGD will not experience miller multiplication. Hence Miller region should not exist. If so, how these equations related to gate charge, CISS, COSS, CRSS, output rise/fall time will look like?
Sir , your video is very useful thanks for me sir ,igbt paller for R C sunbber curcite how to calculated resistance, capacitor value please video created
Thanks for the good video! At 9:18 why does Vd stays high for short period when drain current rises and then starts to drop only when drain current reaches the maximum? What keeps that voltage steady and causes it to fall at exact moment current is at the peak?
Hi Vitaliy, you are welcome and thank you for watching. This is the worse case scenario and Vds might start to fall while Ids is rising. This really depends on the load you are trying to switch and an inductive load will clamp the voltage during the turn-on and turn-off phase because the current through an inductive load can not change instantaneously. And internally Vgs is 0 Volts as Cgs is initially uncharged when you apply the gate-source voltage externally. Therefore at turn-on, you are charging up Cgs and the channel starts to open. For a highly inductive load, you might find that Vds starts to drop before you have current flowing. In all cases, there is an overlap in time between Vdc falling and Ids rising. This overlap results in an instantaneous power that in the worse case (shown here) is triangular shaped. In reality, the instantaneous power might be more parabolic in nature if Vds starts to fall as Ids starts to rise. However, using this worst case is best for designing for power loss and heat dissipation. Unfortunately, turn-on and turn-off is much more messy than this simple graph illustrates. The key take away for design is Qg and trying to determine t-on and t-off. This information will help with sizing your gate driver and determining the switching loss for your application and device. Hope this helps. Best wishes on your design. -Dr K
@@powerelectronicswithdr.k1017 thank you
Thank you so much for your video, I have a question on whether the switching times ( t on and t off ) of the MOSFET vary based on the load condition and the drain to source voltage or not, I know that what mostly controls the switching time characteristics is the gate driving circuit but do other variations like the V_DS and R or L value affect it as well? Thanks in advance!
Tarek, yes to a certain extent the times will change. This is due the Miller capacitance as that charging time will depend on the magnitude of Vds and on the source's ability to provide charge (i.e. higher dq/dt) to the load. It is common to have bulk capacitance across the source, close to the MOSFET bridges that help with supplying charge quickly. In the end, after all your designs and simulations provide some meaningful results, then you will need to build a prototype to test. Another option is to use a topology that is based on softswitching such as the LC or LLC converter, then your switching time, while still important, will not result in large switching losses in the MOSFETs. Hope this helps. -Dr. K
@@powerelectronicswithdr.k1017 Thank you so much for the detailed explanation! I love your content and your dedication to helping Electrical Engineering students all around the world
Mr.K , Do I need to consider gate source capacitance in order to calculate fall time for voltage ?
Sorry Dr.K*
@@my_home_interiors_hyderabad Yes, and also the the gate-drain capacitance. This later will appear larger due to the Miller effect.
Hi, sorry, but in the figure at 6mn, where we can see the turn on of the mosfet, the Ids will reach the load current at starting of Miller flat, but not in the middle like shown by the curves.
Hi, thanks for watching. What you are reference is for an inductive load. This is a resistive load and Ids will reach the full load current at the end of the Miller plateau. The beginning of the Miller plateau is when Vds starts to decline. This voltage will continue to decline as the drain current continues to increase. In an inductive load, the the load will be at full current at the start of the Miller plateau. This is shown at the 9 minute mark of the video.
@@powerelectronicswithdr.k1017
ah OK, right, thanks for your feedback.
Hi Thanks for explanation. I have few questions.
1. In general, what all is the miller capacitance affecting.
Input cap of Mosfet will increase which will affect the previous driver , o/p cap will also increase. Is there any other effect of miller cap.
2. Does bigger plateau or smaller plateau indicate something? What effect will it have on previous stage and on current stage?
Hi Ranjana, the Miller plateau affects the turn -on -off times and is based on the gate-to-drain capacitance. The equivalent capacitance is also dependent on Vds. By “bigger plateau” do you mean the voltage value or the Qgd? Both will impact the turn -on -off times. Here’s a good paper the goes over a first order approximation for determining the switching times for a MOSFET: www.vishay.com/docs/73217/an608a.pdf
Hi, Professor. At 9:54, why does all gate current ig flow through Cgd? I think there is also a path through Cgs. In other words, my question is: Why does the miller plateau exist?
I see the equation ids=gm*(vgs-vth), but it is vgs that determines ids. So even if ids becomes the full load current, vgs can still increase anyway (although it cannot increase the channel current anymore). Is there anything wrong with my thoughts?
@@xinmiaoxu113 Keep in mind voltage doesn't change immediately across a capacitor. When the drain voltage starts to drop, the capacitor effect on Cgd has a negative feedback on the gate voltage, having it stabilized at the Miller plateau. Imagine: if the drain voltage goes low too fast, Vgs will decrease through the Cgd capacitor effect, which would cause the drain voltage to stop dropping or go up again... Gate and drain voltage have opposing effects. That's why there's a voltage which the gate cannot go higher until the drain voltage is stable. That voltage is the Miller plateau.
I failed to understand why there is a flat portion in the graph...what causing physically for which graph is flat....I have never seen any clear cut explanation on this topic (most of the application notes skip this area using some equation )
Hi Biswajit, are you referring to the Miller Plateau? That's the point were the gate-source voltage is constant. During this time of the transition nearly all the gate charge is being used to charge the internal capacitance Cgd. Please refer to page 3 of the following: www.vishay.com/docs/73217/an608a.pdf. This application note provides a good description of the transient behavior of the MOSFET. Best wishes. -Dr. K
7:15 how a current is going from Vg to Vdc if Vdc > Vg
Hi Abbas, great question. This is only for a theoretical pure resistive load. This happens because the node voltage at the drain of the MOSFET is slightly higher (for just a very brief period) than the DC supply voltage. This implies current flowing from the drain (higher potential) to the supply (lower potential). In an actual circuit, this would not happen as the inductance in the load (and leads/traces) will not allow current to flow through the load instantaneously and will clamp that voltage at VDC. Therefore, I wouldn't worry too much about this purely resistive case. Focus more on the Miller plateau and the amount of Q required for turn-on/turn-off. Hope this helps. -Dr K
@@powerelectronicswithdr.k1017 Thank you Dr. K 🤗🤗
Hard to follow the diagram because your pointer is barely visible. Suddenly some drawings appear here and there.
like for beeing pure english