1101 Sequence Detector Verilog Code || Part 1 || Non-Overlapping Mealy FSM ||

[@Footballistaas]

for s11, can you explain the (1/0) 8:04

[@krishnakoli7678]

mealy machine keep getting toggled around s0 & s1 state,
because you didn't introduce next state login in in the code.

[@saizenki]

GG!
For 1101, we are assuming we are reading from MSB to LSB