1101 Sequence Detector Verilog Test Bench || Part 2 || Non-Overlapping Mealy FSM ||

[@CaesarHD]

Thank you sir

[@instinct1098]

Bro taught verilog better than my prof and also under 20mins!! Great explanation!! Btw How are you running verilog in vscode?

[@akshita6478]

indeed!

[@venu_116]

Nice explanation sir

[@riyakhera5665]

How are you able to get state in your waveform?

[@vlsipp]

@riyakhera5665 from xyz_tb.DUT.state