cool video.. thumbs up for the matching. Little suggestion which I knew you are aware already, the output would be better if not crossing the inputs.. but again..this is for demo purpose of matching only. :-)
suppose if there is a separate guard ring for pmos and nmos , and if we do metal connection which passes over the guard ring from pmos guard to nmos guard ring does the connection establishes
There is one pmos and one nmos which are in series, both have separate guard ring, and if we do metal connection for the mosses , were metal passes on guard ring, in these case the connection will be established?
Sir out of curiosity i have a question as u taken fingers in schematic as 8 but when it comes to layout u divide the fingered transistor, then it would a multiplier right then how ur lvs was cleared i didn't understood that one
Hi Sir, I am a B Tech passed out and I am interested in analog layout design. Presently I am at home. I don't want to loose my skills on cadence. How can I design layouts at home? Are there any software for domestic purpose which resembles cadence?
@@khabylameyt5018we can't protect the entire circuit by adding a single guard ring in the top level, because it's a single diode, by adding a Guard ring we protecting each and individual device which makes our entire design in the safer place
Thanks for the wonderful video! I dont have analog experience but I am working in memory layout from 2 years. Can I switch to analog layout?
If you get a chance , switch
@@analoglayout
How do I practise analog layout?do I get any materials to prepare?
Thanks in advance!
cool video.. thumbs up for the matching. Little suggestion which I knew you are aware already, the output would be better if not crossing the inputs.. but again..this is for demo purpose of matching only. :-)
It's just a educational videos , I'm not following any industry standard
suppose if there is a separate guard ring for pmos and nmos , and if we do metal connection which passes over the guard ring from pmos guard to nmos guard ring does the connection establishes
I dont get you point
There is one pmos and one nmos which are in series, both have separate guard ring, and if we do metal connection for the mosses , were metal passes on guard ring, in these case the connection will be established?
Thank you.
You're welcome!
definitely drain connection is connected to out side of the gaurdering or inside guardring
Sir out of curiosity i have a question as u taken fingers in schematic as 8 but when it comes to layout u divide the fingered transistor, then it would a multiplier right then how ur lvs was cleared i didn't understood that one
Ok thank you sir
LVS will check the total area for mosfet , 4*4=16um , so it wont show any LVS problem , bcos schematic and layout having same parameter area wise ..
where is the bulk terminal , which is to be there i am not getting it if we put guard ring, so were the bulk terminal should be
sir put a lecture on lvs and drc errors
How do you do if there needs to be a ground? can we have guard ring for GND also?
What is the purpose of Guard ring? and difference between Fluid guard ring and MPP guard ring
Hello,
I have a doubt
How did you connect the base of two transistors?, where is the base?
This is not a bjt , it's a mos
I believe you are talking about the body of the mosfet. That is connected through a tap cell.
Sir upload opamp. Operation and Resistor matching
resister matching , il upload soon
Analog Layout okk sir
Hi Sir, I am a B Tech passed out and I am interested in analog layout design. Presently I am at home. I don't want to loose my skills on cadence. How can I design layouts at home? Are there any software for domestic purpose which resembles cadence?
You can try tanner or glade , both are free layout editor
Hi sir in this why keep gate connectio routing some far from source and drain
to reduce coupling from source & drain over gate
Sir how do we connect the bulk terminal?, answer please, thanks
By using guard ring we will connect bulk connection
Okay, so the bulks were already shorted to the sources?
I finally understood haha
@@analoglayout so we use guard ring just for bulks
Or we use it also for protect the circuit
@@khabylameyt5018we can't protect the entire circuit by adding a single guard ring in the top level, because it's a single diode, by adding a Guard ring we protecting each and individual device which makes our entire design in the safer place
is this schematic rely on [tsmc 18]?
I think it's tsmc65
Why you don't use the align tool?????
Some time il use ...
psubstrate_StampErrorFloat i cant solve this. anybody help please
Check the subtract connection once
no add to dummy in this layout, y
dummy we need add , already this video took 35 min, so i didn't add dummy , already i uploaded a video , how to add dummy , pls watch that ..
ERC error ?
this videos for educational purpose , i'm not designing for real time chip , so i didn't chk ERC , and few checks