hey , why isnt Cint of the pmos also considered for the last part (only Cl)? also why isnt Cl considered for the path of the one nmos that is in the path below?
@@arnabratna5536 This is called overshoot/undershoot. This is due to capacitive coupling that will bring the voltage to be lower than ground or higher than Vdd.
this is an example of capacitive coupling th-cam.com/video/CLiwnGWlBmc/w-d-xo.htmlfeature=shared&t=1140 (but it is not for this case. However, it illustrate the idea)
hey , why isnt Cint of the pmos also considered for the last part (only Cl)? also why isnt Cl considered for the path of the one nmos that is in the path below?
Can you let me know which slide you are referring to? Thanks!
Output voltage making a hook before going up why does that down side coming?
Can you let me know which slide and figure you are referring to? Thanks!
Sir on slide 9, V vs time fig
@@arnabratna5536 This is called overshoot/undershoot. This is due to capacitive coupling that will bring the voltage to be lower than ground or higher than Vdd.
this is an example of capacitive coupling th-cam.com/video/CLiwnGWlBmc/w-d-xo.htmlfeature=shared&t=1140 (but it is not for this case. However, it illustrate the idea)