17:04 For Fall Contamination Delay, When Node X is allready been discharged , then voltage across it should be zero and it should short the equivalent R/2 resistance. Therefore , 6C will face only Upper R/2 resistance to get discharged.!!!! Then delay should be only 6C×R/2 = 3RC!!!
This is not true. first of all, caps in DC analysis are not shorted but "open". second, eventually in steady state both parasitic capacitances will be discharged. in other words, current will flow from the caps through the resistors to the ground.
No it must be R/3. Because he has sized the PMOS transistors as 6. 2 units of width in PMOS gives a resistance of R. 6 = 2*3 units of width will give a resistance of R/3 as the resistance is inversely proportional to the width of the transistor.
@@raj.dpatel1162 according to Elmore delay top capacitor(=6C) discharges through resistors R/2 and R/2, bottom capacitor can discharge through bottom resistor R/2 alone. so the eqn becomes 6C(R/2+R/2)+2C(R/2)=7RC
you should separate it into two parts. one is the path from the top cap right to the ground (2*r/2 resistors) and second is from the bottom cap to the ground (r/2 resistor). therefore, 6C*(2*r/2) + 2C*r/2 = 7RC
This series has been very helpful in understanding all the concepts clearly
17:04 For Fall Contamination Delay, When Node X is allready been discharged , then voltage across it should be zero and it should short the equivalent R/2 resistance.
Therefore , 6C will face only Upper R/2 resistance to get discharged.!!!!
Then delay should be only 6C×R/2 = 3RC!!!
This is not true.
first of all, caps in DC analysis are not shorted but "open".
second, eventually in steady state both parasitic capacitances will be discharged. in other words, current will flow from the caps through the resistors to the ground.
DURING RISE TIME (PROP & CONT.)
THE RESISTANCE SHOULD BE R/2 RYT WHILE CALCULATING THE PROPAGATION DELAY?
yes , i also thought that same thing.
No it must be R/3. Because he has sized the PMOS transistors as 6. 2 units of width in PMOS gives a resistance of R. 6 = 2*3 units of width will give a resistance of R/3 as the resistance is inversely proportional to the width of the transistor.
For NOR 3 GATE , How rise contamination delay becomes 9RC..?.
ARE both 6C fully charged to Vdd..?
Yes, going by what he said, A and B are low for long enough for the 6C caps to be charged to VDD>
How it is 7Rc for the case when X and y both need to get discharge ??
@Parmider Kaur use Elmore delay model it's (RC+6RC) total 7RC
@@naveen6838 could you please explain me
@@raj.dpatel1162 according to Elmore delay top capacitor(=6C) discharges through resistors R/2 and R/2, bottom capacitor can discharge through bottom resistor R/2 alone. so the eqn becomes 6C(R/2+R/2)+2C(R/2)=7RC
How we get 7RC delay
you should separate it into two parts. one is the path from the top cap right to the ground (2*r/2 resistors) and second is from the bottom cap to the ground (r/2 resistor). therefore, 6C*(2*r/2) + 2C*r/2 = 7RC
@@ofek2852 thx