How to use the 'stable attribute for checking setup and hold times and pulse widths of VHDL signals

Did you know that VHDL signals have a built-in feature for verifying that the value hasn't changed for a given time?
I often use the 'stable attribute for verifying setup and hold times on asynchronous interfaces. For example, the CS / SCLK relationship shown in the video.
The syntax for using 'stable is:
signal_name'stable(time_value)
And it will return a boolean value. It returns true if the signal's value hasn't changed before the current simulation time for the given period. And it returns false if it has changed at least once during that time.
Thus, you can use it within an assert statement to verify timing requirements, as shown in the code below.
process
begin
wait until cs = '0' and falling_edge(sclk);
assert cs'stable(10 ns)
report "Falling SCLK too close to falling CS"
severity failure;
end process;
But can we use it to check pulse widths too? Yes! But then we need to use a helper signal and take advantage of the delta cycles delays that VHDL simulators use to model inter-process communication.
Check out the video to see the other way to use the 'stable attribute in VHDL testbenches!
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[@TheStrelok7]

Thank you very much, informative video!