Hi, May I know why is PGD_ON pst state is required? In starting there is a req as"Logic inside aon_pgd_wrapper can be power gated but won’t be power gated when pgd_wrapper is powered ON."
Hi Samhitha, thank you for pointing it out. PGD_ON pst state is not required as it contradicts the assumption (I might have included it to consider all the 4 possible states of VDDH_gated and VDDL_gated as if it is a truth table). I will pin your comment so that everyone will know. Also, I have not included GND in the power state (an user named __RMK__ pointed it out in the comments)
Thank you for your insights! I have just started learning about UPF, may I know why GND was not included in create_pst command along with VCCH, VCCL, VCCH_gated and VCCL_gated?
Apologies for the late reply. Thanks for pointing it out (I might have ignored it because it is ground). But we need to specify the value GND can take on before using it in create_pst, like this - add_port_state GND -state {gnd 0.0}
perfectly explained..nowhere on internet found such a beautiful detailed explanation of this complex topic..I take many ideas from your video to present in my office ppt on this research topic..Thanks and keep updating such topics in a detailed way like you do..:)
Nice explanation..Keep it up.. You have posted one video. Request you to please do post more videos. There are lot of folks needing guidance in VLSI....Thanks for the effort...
Thank you, I am glad you find it useful. Making videos, especially putting together slides for presentation takes a lot of effort; due to work and personal commitments, I am not able to make more videos. However you can visit my blog vlsitutorials.com to check out other topics.
Thanks for creating this helpful video! When we do power analysis using let's say PrimePower and load this UPF, can we tell PrimePower to calculate power for a particular power state?
Very well explained, I wanted to ask specific questions given a particular design and implementation. Is there any way I can discuss with you directly?
Hi， I load the UPF script with Design Compiler, and find a ERROR message "Error: The supply net VCCH specified for the isolation strategy isol_sig_from_aon_pgd does not exist in the power domain pd_aon in which the isolation cells will be inserted. (UPF-103)", I think this is because the location of "isol_sig_from_aon_pgd" is parent, and this isolation will be inserted to pd_aon domain, but in which this is no VCCH supply net, so it causes a error.
Karan Praba I am glad you find it helpful. I am not sure if any site has this information. May be I will try to write a RTL corresponding to this UPF and update in my blog. But if you want to learn about upf command syntax and other information, you can check here - vlsitutorials.com/upf-command-syntax-low-power-vlsi/ vlsitutorials.com/power/
Hi Robin, I am glad you find it useful. I don’t want to make a video about CDC as there are plenty of good videos about it on youtube, please refer those. :) However I may be uploading a video about Scan and ATPG concepts in near future.
@@vlsitutorials3484 Thanks. That(scan/ATPG ) will be great. Basically I didn't find any good videos which explain cdc constraints like how you explained STA constraints in your blog. I found it's very clearly explained in your blog.
Hi, May I know why is PGD_ON pst state is required? In starting there is a req as"Logic inside aon_pgd_wrapper can be power gated but won’t be power gated when pgd_wrapper is powered ON."
Hi Samhitha, thank you for pointing it out. PGD_ON pst state is not required as it contradicts the assumption (I might have included it to consider all the 4 possible states of VDDH_gated and VDDL_gated as if it is a truth table). I will pin your comment so that everyone will know.
Also, I have not included GND in the power state (an user named __RMK__ pointed it out in the comments)
Really appreciate your explanation dude, I'm just starting to write some UPF files and it really helps to quickly ramp up.
Luxen Belmont You’re welcome. I’m glad it helped you.
Thank you very much for the explanation, it is very clear and covers multiple useful features
Very nice...
nice explanation👏
Thank you for your insights! I have just started learning about UPF, may I know why GND was not included in create_pst command along with VCCH, VCCL, VCCH_gated and VCCL_gated?
Apologies for the late reply. Thanks for pointing it out (I might have ignored it because it is ground). But we need to specify the value GND can take on before using it in create_pst, like this -
add_port_state GND -state {gnd 0.0}
perfectly explained..nowhere on internet found such a beautiful detailed explanation of this complex topic..I take many ideas from your video to present in my office ppt on this research topic..Thanks and keep updating such topics in a detailed way like you do..:)
Thank you Kirti. :) You can refer my website for other topics of your interest vlsitutorials.com
Nice explanation..Keep it up.. You have posted one video. Request you to please do post more videos. There are lot of folks needing guidance in VLSI....Thanks for the effort...
Thank you, I am glad you find it useful. Making videos, especially putting together slides for presentation takes a lot of effort; due to work and personal commitments, I am not able to make more videos. However you can visit my blog vlsitutorials.com to check out other topics.
Very resourceful and concise. Thanks a Lot For Sharing :)
Thanks for creating this helpful video! When we do power analysis using let's say PrimePower and load this UPF, can we tell PrimePower to calculate power for a particular power state?
Hi Amit, I am glad you liked it. Unfortunately I have not worked on power analysis therefore I will not be able to comment.
Very well explained, I wanted to ask specific questions given a particular design and implementation. Is there any way I can discuss with you directly?
Thank you. I have already replied to your mail.
Really appreciate your effort
Thank you
Hi, may I know why sig3 donnot need ISO cell? Because pd_gated_aon domain also may turn-off power
Thansk a lot for the video :) that was a very good explanation of UPF
Awesome explanation. Very surprising that there is no like for such an informative video :( +1 Like
Thank you :). You can go through my blog for other information.
Hi， I load the UPF script with Design Compiler, and find a ERROR message "Error: The supply net VCCH specified for the isolation strategy isol_sig_from_aon_pgd does not exist in the power domain pd_aon in which the isolation cells will be inserted. (UPF-103)", I think this is because the location of "isol_sig_from_aon_pgd" is parent, and this isolation will be inserted to pd_aon domain,
but in which this is no VCCH supply net, so it causes a error.
Really good explanation . Actually, I am trying to learn the UPF basics. Is there any web link, that I can find the example RTL, UPF for the same .
Karan Praba I am glad you find it helpful. I am not sure if any site has this information. May be I will try to write a RTL corresponding to this UPF and update in my blog. But if you want to learn about upf command syntax and other information, you can check here -
vlsitutorials.com/upf-command-syntax-low-power-vlsi/
vlsitutorials.com/power/
how to add a power mode in upf
i know how to add in cpf but dont know how to add to upf
Super
Nice vedio, very helpful
Thanks
Is this ever needed for FPGAs?
Your website does not seem to be working. It would be very helpful if you restart it.
Niraj Patil It is working fine. Please check.
vlsitutorials.com/power/
For other topics click on the ‘menu’ button in the website.
Impressive. Please make a video for the CDC also.
Hi Robin, I am glad you find it useful. I don’t want to make a video about CDC as there are plenty of good videos about it on youtube, please refer those. :) However I may be uploading a video about Scan and ATPG concepts in near future.
@@vlsitutorials3484 Thanks. That(scan/ATPG ) will be great. Basically I didn't find any good videos which explain cdc constraints like how you explained STA constraints in your blog. I found it's very clearly explained in your blog.
thanks
nice one. Can I get your email?
You can drop a mail at vlsitutorials@gmail.com