Hi Rahul, the target latency and skew are set by the clock design team. During Clock Tree synthesis these will be used. Clock design team reviews different types of trees that can be implemented. They use the best type for the particular type of design. There's always a trade of between skew and latency since adding additional buffers leads to insertion delay. But it's not true that always 0 skew is best. 0 skew may result in hotspot of high local IR drop. So, considering these power and reliability issues and timing issues those are set and designed.
Hi Sir, I have query regarding cts, that i have seen cts builds in nominal corner and after that optimization is happening in fast and slow corner. Why there is a preference of nominal corner over fast or slow.
Hi, I want to know one thing.. during hold time clk is high.. and input can be passed through the transistor when clk is low. So during hold time even if data changes then also it can't reach to output because it can be passed through the transistor when clk is low
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Hi sir, Could you please explain how we decide target latency and target skew for a block.
Hi Rahul, the target latency and skew are set by the clock design team. During Clock Tree synthesis these will be used. Clock design team reviews different types of trees that can be implemented. They use the best type for the particular type of design. There's always a trade of between skew and latency since adding additional buffers leads to insertion delay. But it's not true that always 0 skew is best. 0 skew may result in hotspot of high local IR drop. So, considering these power and reliability issues and timing issues those are set and designed.
Hi Sir, I have query regarding cts, that i have seen cts builds in nominal corner and after that optimization is happening in fast and slow corner. Why there is a preference of nominal corner over fast or slow.
You have mentioned the hold equation the opposite way. T(clk-q) + T(comb) > T(hold)
Where ? He has mentioned as per your message : T(clk-q) + T(comb) > T(hold)
Hi,
I want to know one thing.. during hold time clk is high.. and input can be passed through the transistor when clk is low. So during hold time even if data changes then also it can't reach to output because it can be passed through the transistor when clk is low
Please answer this question. I also having the same doubt.