ROM Read Only Memory RTL Code in Verilog and VHDL with Testbench. Read hex data from input file

#ROM Read Only Memory Design #RTL #Code in #Verilog and #VHDL with #Testbench. #Read #hex #data from #input #file
ROM SV RTL code:
module program_rom(pc, code);
output [15:0] code;
input [7:0] pc;
reg [15:0] rom[255:0];
initial
begin
// rom[0] = 16'h0000;// with rom as reg
// rom[1] = 16'h1111;
// rom[2] = 16'h2222;
// rom[3] = 16'h3333;
// rom[4] = 16'h4444;
// rom[5] = 16'h5555;
// rom[6] = 16'h6666;
// rom[7] = 16'h7777;
// rom[8] = 16'h8888;
// rom[9] = 16'h9999;
// rom[10] = 16'hffff;
$readmemh("test.hex", rom);
end
assign code = rom[pc];
endmodule // program_rom
ROM SV testbench:
module test_bench;
reg [7:0] pc;
wire [15:0] code;
integer i;
program_rom uut(pc, code);
initial begin
//pc = 8'h00;
pc = 8'b00000000;
#10;
for (i = 1;i ＜= 10;i = i + 1)
begin
//pc = pc + 8'h01;
pc = pc + 8'b00000001;
#10;
end;
end
endmodule
ROM VHDL RTL code:
library ieee,std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;--for conv_integer
use std.textio.all;-- for text, line, readline, endfile
use ieee.std_logic_textio.all;-- for hread
entity program_rom is
port ( pc: in std_logic_vector(7 downto 0);
code: out std_logic_vector(15 downto 0));
end program_rom;
architecture str of program_rom is
type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0);
signal rom: rom_type;
begin
-- rom(10)＜= x"FFFF";
-- rom(9)＜= x"9999";
-- rom(8)＜= x"8888";
-- rom(7)＜= x"7777";
-- rom(6)＜= x"6666";
-- rom(5)＜= x"5555";
-- rom(4)＜= x"4444";
-- rom(3)＜= x"3333";
-- rom(2)＜= x"2222";
-- rom(1)＜= x"1111";
-- rom(0)＜= x"0000";
process
file fin : text open read_mode is "test.hex";
variable rdline : line;
variable WORD : std_logic_vector(15 downto 0);
begin
for i in 0 to 255 loop
readline(fin, rdline);
hread(rdline, WORD);
rom(i) ＜= WORD;
if endfile(fin) then
exit;
end if;
end loop;
wait;
end process;
code ＜= rom(conv_integer(pc));
----use std_logic_vector pc as index for rom array
end str;
ROM VHDL testbench:
-- testbench for rom
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;-- for +
entity test_bench is
end test_bench;
architecture behav of test_bench is
component program_rom is
port ( pc: in std_logic_vector(7 downto 0);
code: out std_logic_vector(15 downto 0));
end component;
signal code : std_logic_vector (15 downto 0);
signal pc: std_logic_vector ( 7 downto 0);
begin
uut:program_rom port map (pc, code);
stim_proc:process
begin
pc ＜= "00000000";
--pc ＜= x"00";
wait for 10 ns;
for i in 1 to 10 loop
pc ＜= pc + "00000001";
--pc ＜= pc + x"01";
wait for 10 ns;
end loop;
wait;
end process;
end behav;
Hex input file:
0000
1111
2222
3333
4444
5555
6666
7777
8888
9999
ffff

[@ArifMahmood]

ROM RTL SV code:
github.com/aarifboy/verilogvsvhdl/blob/main/rom_sv_input_file.sv
ROM RTL SV testbench:
github.com/aarifboy/verilogvsvhdl/blob/main/test_rom_input_file.sv
ROM RTL VHDL code:
github.com/aarifboy/verilogvsvhdl/blob/main/rom_vhdl_input_file.vhd
ROM RTL VHDL testbench:
github.com/aarifboy/verilogvsvhdl/blob/main/test_rom_input_file.vhd
Hex Input file:
github.com/aarifboy/verilogvsvhdl/blob/main/test.hex