Arif Mahmood
Arif Mahmood
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  • 228 970
Make a Cheap Pocket Hand Chainsaw. Manual Saw Tool to Cut Trees Effectively Fast. An Amazing Gadget
#Make a #Cheap #Pocket #Hand #Chainsaw. #Manual #Saw #Tool to #Cut #Trees #Effectively #Fast. An #Amazing #Woodcutter #Gadget. This saw wont #get #stuck in the #wood
มุมมอง: 309

วีดีโอ

Apple Garden Trees in Germany (Dusslingen).2:51Apple Garden Trees in Germany (Dusslingen).
Apple Garden Trees in Germany (Dusslingen).
มุมมอง 46ปีที่แล้ว
#Apple #Garden #Trees in #Germany (#Dusslingen).
CSA Carry Select Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model22:38CSA Carry Select Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model
CSA Carry Select Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model
มุมมอง 476ปีที่แล้ว
#CSA #Carry #Select #Adder 8 bit #Code with #Overflow in #Verilog and #VHDL with #Testbench. #Structural #model SV RTL code: module adder(s, co, a, b, ci); output s, co; input a, b, ci; // wire [1:0] Result; // assign Result = a b ci; // assign s = Result[0]; // assign co = Result[1]; assign {co,s} = a b ci; endmodule // adder module mux2to1(in0, in1, sel, out); output out; input in0, in1, sel;...
Carry Look-Ahead Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model26:25Carry Look-Ahead Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model
Carry Look-Ahead Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model
มุมมอง 895ปีที่แล้ว
#CLA #Carry #Look-Ahead #Adder 8 bit #Code with #Overflow in #Verilog and #VHDL with #Testbench. #Structural #modeling SV RTL code: module xor_1(s, a, b); output s; input a,b; assign s = a ^ b; endmodule // xor_1 // structural model of half_adder module half_adder(s, c, a, b); output s, c; input a, b; assign s = a ^ b; assign c = a & b; endmodule // half_adder //behavioral model of level 1 cla ...
Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model.22:56Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model.
Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model.
มุมมอง 1.4Kปีที่แล้ว
#Full #Adder/#Subtractor 8 #bit #Code with #Overflow in #Verilog and #VHDL with #Testbench. #Structural #Model. SV RTL code: module xor_1(s, a, b); output s; input a,b; assign s = a ^ b; endmodule // xor_1 module adder_8(s, co, ofl, a, b, ci); output [7:0] s; output co, ofl; input [7:0] a, b; input ci; assign s = a b ci; assign co = (a[7] & b[7])|(a[7] & ~s[7])|(b[7] & ~s[7]); assign ofl = (a[7...
Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Behavioral Model.28:21Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Behavioral Model.
Full Adder/Subtractor 8 bit Code with Overflow in Verilog and VHDL with Testbench. Behavioral Model.
มุมมอง 325ปีที่แล้ว
#Full #Adder/#Subtractor #8 #bit Code with #Overflow in #Verilog and #VHDL with #Testbench. #Behavioral #Model. SV RTL code: module addsub_8(s, co, ofl, a, b, sub); output [7:0] s; output co, ofl; input [7:0] a, b; input sub; //wire [7:0] xb; wire [8:0] Result; // assign xb[0] = b[0] ^ sub; // assign xb[1] = b[1] ^ sub; // assign xb[2] = b[2] ^ sub; // assign xb[3] = b[3] ^ sub; // assign xb[4]...
Carry Ripple Adder 8 bit RTL Code with Overflow in Verilog & VHDL with Testbench. Structural Model.28:24Carry Ripple Adder 8 bit RTL Code with Overflow in Verilog & VHDL with Testbench. Structural Model.
Carry Ripple Adder 8 bit RTL Code with Overflow in Verilog & VHDL with Testbench. Structural Model.
มุมมอง 244ปีที่แล้ว
#Carry #Ripple #Adder 8 bit #RTL #Code with #Overflow in #Verilog & #VHDL with #Testbench. #Structural #Model. SV RTL code: module xor_1(s, a, b); output s; input a,b; //assign s = a ^ b); assign s = a!=b ? 1'b1:1'b0; endmodule // xor // module adder(s, co, a, b, ci); output s, co; input a, b, ci; wire [1:0] Result; assign Result = a b ci; assign s = Result[0]; assign co = Result[1]; endmodule ...
Full Adder 8 bit RTL Code with Carry & Overflow in Verilog & VHDL with Testbench. Behavioral Model.20:35Full Adder 8 bit RTL Code with Carry & Overflow in Verilog & VHDL with Testbench. Behavioral Model.
Full Adder 8 bit RTL Code with Carry & Overflow in Verilog & VHDL with Testbench. Behavioral Model.
มุมมอง 235ปีที่แล้ว
#FA #Full #Adder 8 bit #RTL #Design #Code with #carry and #overflow in #Verilog and #VHDL with #Testbench. Using #Behavioral #Modeling. SV RTL code: //behavioral model module adder_8(s, co, of, a, b, ci); output [7:0] s; output co, of; input [7:0] a, b; input ci; wire [8:0] Result; //assign {co, s} = a b ci; //assign s = a b ci; //assign co = (a[7] & b[7])|(a[7] & ~s[7])|(b[7] & ~s[7]); assign ...
Write RTL Testbench to Display Output on Console Window in Verilog and VHDL. Break/Exit Simulation41:59Write RTL Testbench to Display Output on Console Window in Verilog and VHDL. Break/Exit Simulation
Write RTL Testbench to Display Output on Console Window in Verilog and VHDL. Break/Exit Simulation
มุมมอง 80ปีที่แล้ว
#Write #RTL #Testbench to #Display #Output on #Console/#Transcript #Window in #Verilog and #VHDL. #Break/#Exit #simulation SV RTL testbench: module testbench; reg stop; reg [15:0] cycles; initial begin stop = 1'b0; cycles = 16'b0; $timeformat(-9, 2, " ns", 15); // to display ns with time end always @(negedge clk) begin cycles ＜= cycles 1; if (stop) begin //$display("Time:%t Instance: /%m ",$tim...
PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.26:15PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.
PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.
มุมมอง 142ปีที่แล้ว
#PC #Program #Counter 8 bit #RTL #Design #Code in #Verilog and #VHDL with #Testbench. #Using #Structural #Modeling. SV PC RTL code: module dff_8(d, clk, q); output [7:0] q; input [7:0] d; input clk; reg [7:0] q; always @(posedge clk) q ＜= d; endmodule // dff_8 module inc_8(s, a); output [7:0] s; input [7:0] a; assign s = a 1; endmodule // inc_8 module mux2to1_8(in0, in1, sel, out); output [7:0]...
PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.23:45PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
PC Program Counter 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
มุมมอง 474ปีที่แล้ว
#PC #Program #Counter 8 bit #RTL #Design #Code in #System #Verilog and #VHDL #with #Testbench. #Using #Behavioral #Modeling. SV PC RTL code: // PC: program counter //behavioral model module P_C(pc, power, clk, branch_pc, branch_en, stop_en, next_pc); output [7:0] pc, next_pc; input power, clk, branch_en, stop_en; input [7:0] branch_pc; reg [7:0] pc; wire [7:0] inc_pc, temp_pc0, temp_pc1; always...
SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Model22:16SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Model
SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Model
มุมมอง 112ปีที่แล้ว
#SRA #Arithmetic #Shift #Right 8 bit #RTL #Code in #Verilog and #VHDL with #Testbench. #Using #Structural #modeling SV SRA RTL code: module mux2to1_8(in0, in1, sel, o); output [7:0] o; input [7:0] in0, in1; input sel; assign o = sel? in1:in0;//data flow modeling/continuous assignment endmodule // mux2to1_8 // structural model shift right logic b is 2:0 for sra module shift_right_arithmetic_8(s,...
SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Model24:48SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Model
SRA Arithmetic Shift Right 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Model
มุมมอง 133ปีที่แล้ว
#SRA #Arithmetic #Shift #Right 8 bit #RTL #Code in #Verilog and #VHDL with #Testbench. #Using #Behavioral #model SV SRA RTL code: // behavioral model shift right logic b is 2:0 for sra module shift_right_arithmetic_8(s, a, b); output [7:0] s; input [7:0] a, b; wire [7:0] s1, s2; //assign s = $signed(a) ＞＞＞ b[2:0]; // reg [7:0] s; // always@(*) // begin // if (b[2:0] 0) // s = a; // else if (b[2...
ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Structural Modeling18:14ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Structural Modeling
ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Structural Modeling
มุมมอง 185ปีที่แล้ว
#ROR #Rotate #Right 8 bit #RTL #Design #Code in #Verilog and #VHDL with #Testbench. #Using #Structural Modeling SV ROR RTL code: module mux2to1_8(in0, in1, sel, out); output [7:0] out; input [7:0] in0, in1; input sel; assign out = sel? in1:in0;//data flow modeling/continuous assignment endmodule // mux2to1_8 // behavioral model rotate right b is 2:0 for ror module rotate_right_8(s, a, b); outpu...
ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Behavioral Modeling30:54ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Behavioral Modeling
ROR Rotate Right 8 bit RTL Design Code in Verilog and VHDL with Testbench. Using Behavioral Modeling
มุมมอง 66ปีที่แล้ว
#ROR #Rotate #Right 8 bit #RTL #Design #Code in #Verilog and #VHDL with #Testbench. Using #Behavioral #modeling SV ROR RTL code: // behavioral model rotate right b is 2:0 for ror module rotate_right_8(s, a, b); output [7:0] s; input [7:0] a, b; wire [7:0] s1, s2; // // reg [7:0] s; // //always@(a or b) // always@(*) // begin // if (b[2:0] 0) // s = a;//000 // else if (b[2:0] 1) // s = {a[0],a[7...
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.20:44SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.
มุมมอง 188ปีที่แล้ว
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Structural Modeling.
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.28:45SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
มุมมอง 113ปีที่แล้ว
SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.
Fix Verilog Simulation Warning: (vsim-2685) [TFMPC] Expected . found ..(vsim-3722) [TFMPC] missing5:33Fix Verilog Simulation Warning: (vsim-2685) [TFMPC] Expected . found ..(vsim-3722) [TFMPC] missing
Fix Verilog Simulation Warning: (vsim-2685) [TFMPC] Expected . found ..(vsim-3722) [TFMPC] missing
มุมมอง 55ปีที่แล้ว
Fix Verilog Simulation Warning: (vsim-2685) [TFMPC] Expected . found ..(vsim-3722) [TFMPC] missing
ROM Read Only Memory RTL Code in Verilog and VHDL with Testbench. Read hex data from input file16:34ROM Read Only Memory RTL Code in Verilog and VHDL with Testbench. Read hex data from input file
ROM Read Only Memory RTL Code in Verilog and VHDL with Testbench. Read hex data from input file
มุมมอง 244ปีที่แล้ว
ROM Read Only Memory RTL Code in Verilog and VHDL with Testbench. Read hex data from input file
ROM Read Only Memory Design RTL Code in Verilog and VHDL with Testbench17:13ROM Read Only Memory Design RTL Code in Verilog and VHDL with Testbench
ROM Read Only Memory Design RTL Code in Verilog and VHDL with Testbench
มุมมอง 284ปีที่แล้ว
ROM Read Only Memory Design RTL Code in Verilog and VHDL with Testbench
MACRO ..verilog.do PAUSED at line ...Fix Quartus Error: Module '..' does not have a timeunit/timepre6:57MACRO ..verilog.do PAUSED at line ...Fix Quartus Error: Module '..' does not have a timeunit/timepre
MACRO ..verilog.do PAUSED at line ...Fix Quartus Error: Module '..' does not have a timeunit/timepre
มุมมอง 190ปีที่แล้ว
MACRO ..verilog.do PAUSED at line ...Fix Quartus Error: Module '..' does not have a timeunit/timepre
Compile and Run Functional Simulation in Quartus for Verilog and VHDL RTL Codes without a Testbench15:59Compile and Run Functional Simulation in Quartus for Verilog and VHDL RTL Codes without a Testbench
Compile and Run Functional Simulation in Quartus for Verilog and VHDL RTL Codes without a Testbench
มุมมอง 307ปีที่แล้ว
Compile and Run Functional Simulation in Quartus for Verilog and VHDL RTL Codes without a Testbench
Fix Quartus error: vsim-12110 all optimizations are disabled because the -novopt option is in effect2:39Fix Quartus error: vsim-12110 all optimizations are disabled because the -novopt option is in effect
Fix Quartus error: vsim-12110 all optimizations are disabled because the -novopt option is in effect
มุมมอง 974ปีที่แล้ว
Fix Quartus error: vsim-12110 all optimizations are disabled because the -novopt option is in effect
Compile and Run Simulation in Quartus Prime for Verilog and VHDL RTL Codes with Testbench and Questa18:46Compile and Run Simulation in Quartus Prime for Verilog and VHDL RTL Codes with Testbench and Questa
Compile and Run Simulation in Quartus Prime for Verilog and VHDL RTL Codes with Testbench and Questa
มุมมอง 2.5Kปีที่แล้ว
Compile and Run Simulation in Quartus Prime for Verilog and VHDL RTL Codes with Testbench and Questa
Compile and Run Simulation in Questa - Intel FPGA for Verilog and VHDL RTL Codes with Testbench26:40Compile and Run Simulation in Questa - Intel FPGA for Verilog and VHDL RTL Codes with Testbench
Compile and Run Simulation in Questa - Intel FPGA for Verilog and VHDL RTL Codes with Testbench
มุมมอง 396ปีที่แล้ว
Compile and Run Simulation in Questa - Intel FPGA for Verilog and VHDL RTL Codes with Testbench
Fix Nativelink Error missing ". Check NativeLink log file. Open Questa from Quartus RTL Simulation5:37Fix Nativelink Error missing ". Check NativeLink log file. Open Questa from Quartus RTL Simulation
Fix Nativelink Error missing ". Check NativeLink log file. Open Questa from Quartus RTL Simulation
มุมมอง 3.1Kปีที่แล้ว
Fix Nativelink Error missing ". Check NativeLink log file. Open Questa from Quartus RTL Simulation
Fix VHDL Function Error Unknown identifier "to_hstring in Questa during compile of RTL code2:25Fix VHDL Function Error Unknown identifier "to_hstring in Questa during compile of RTL code
Fix VHDL Function Error Unknown identifier "to_hstring in Questa during compile of RTL code
มุมมอง 281ปีที่แล้ว
Fix VHDL Function Error Unknown identifier "to_hstring in Questa during compile of RTL code
Most Frequent/Occurring element in an Array in c++ and c# With/Without Unordered_map/Dictionary 7623:16Most Frequent/Occurring element in an Array in c++ and c# With/Without Unordered_map/Dictionary 76
Most Frequent/Occurring element in an Array in c++ and c# With/Without Unordered_map/Dictionary 76
มุมมอง 2072 ปีที่แล้ว
Most Frequent/Occurring element in an Array in c and c# With/Without Unordered_map/Dictionary 76
Calculate/Find Factorial of an Integer Number in c++ and c# Using Recursive and Iterative Methods 7510:47Calculate/Find Factorial of an Integer Number in c++ and c# Using Recursive and Iterative Methods 75
Calculate/Find Factorial of an Integer Number in c++ and c# Using Recursive and Iterative Methods 75
มุมมอง 322 ปีที่แล้ว
Calculate/Find Factorial of an Integer Number in c and c# Using Recursive and Iterative Methods 75
Calculate/Find Factorial of an Integer Number in c and c++ Using Recursive and Iterative Methods 2211:31Calculate/Find Factorial of an Integer Number in c and c++ Using Recursive and Iterative Methods 22
Calculate/Find Factorial of an Integer Number in c and c++ Using Recursive and Iterative Methods 22
มุมมอง 452 ปีที่แล้ว
Calculate/Find Factorial of an Integer Number in c and c Using Recursive and Iterative Methods 22

ความคิดเห็น

  • @khaledelsayed3507
    @khaledelsayed3507 หลายเดือนก่อน

    thank you

  • @muhammadmassabhashmi5961
    @muhammadmassabhashmi5961 หลายเดือนก่อน

    Carrier or box ko mila k kitni price me mila ap ko?

    • @ArifMahmood
      @ArifMahmood หลายเดือนก่อน

      Video ko dhyan se dekho

    • @muhammadmassabhashmi5961
      @muhammadmassabhashmi5961 หลายเดือนก่อน

      @@ArifMahmood g sir ap agr English k bajae apni qomi zoban me baat krte to moje tajziya krne ki zrorat b nhi thy

    • @ArifMahmood
      @ArifMahmood หลายเดือนก่อน

      @@muhammadmassabhashmi5961 price tau sab english mein hee batatey hain

  • @AliRaza-cr5xx
    @AliRaza-cr5xx 2 หลายเดือนก่อน

    Gando urdo men bt kro Pakistan men bharwy

  • @manjulag6847
    @manjulag6847 3 หลายเดือนก่อน

    These setting does not show in quartus version 13.1

  • @zishansharif2001
    @zishansharif2001 4 หลายเดือนก่อน

    پرا گڈی زبردست باکس زبردست بس تساں اردو ہی بول لو😂

  • @laminmandorry788
    @laminmandorry788 4 หลายเดือนก่อน

    Thank you I have been trying to debug this for few days now

  • @junaidjutt179
    @junaidjutt179 4 หลายเดือนก่อน

    Kindly information, IAM buying

  • @ArifMahmood
    @ArifMahmood 5 หลายเดือนก่อน

    @18:30 "Build a Story Map" this option is no longer available. Instead @37:15 click on "Create Web App" and choose option ArcGIS StoryMaps

  • @rodrigoapaza8086
    @rodrigoapaza8086 6 หลายเดือนก่อน

    Muchas gracias :D

  • @raohammad6290
    @raohammad6290 9 หลายเดือนก่อน

    what if i want it to be a csv?

  • @jwp1002
    @jwp1002 10 หลายเดือนก่อน

    Thank you for posting this! I am new to Quartus / Questa and was lost by this error.

  • @joaoabrunhosa3474
    @joaoabrunhosa3474 10 หลายเดือนก่อน

    THANKS YOU SO MUCH

  • @ChristopherFourati
    @ChristopherFourati 10 หลายเดือนก่อน

    Just helped me aswell. Thanks alot for finding and sharing!

  • @ananddsavant6130
    @ananddsavant6130 11 หลายเดือนก่อน

    I followed your steps. But at the end when I click on run simulation.. the questa isn't opening.. pls help

  • @coderhex1675
    @coderhex1675 ปีที่แล้ว

    this is RIDICULUS, we are talking about Intel

  • @EvanVance-j8j
    @EvanVance-j8j ปีที่แล้ว

    Yes my locks fell out they replaced them under warranty and the new ones fell out too. The Lid caught now the box is warped. They want way too much money for these boxes.

  • @benceszilagyi-ppe
    @benceszilagyi-ppe ปีที่แล้ว

    How in the actual hell does Intel miss a closing quotation mark in a default install file?

  • @卢子沛
    @卢子沛 ปีที่แล้ว

    What a rediculous bug😂. Anyway, your guide is amazing, thanks a lot.

  • @ItzAis.
    @ItzAis. ปีที่แล้ว

    Huge help! Thanks! For anyone that can't read from the video, replace "novopt" with "voptargs="+acc" "

  • @ViniciusSchoffenTonello
    @ViniciusSchoffenTonello ปีที่แล้ว

    Hi when i create another waveform file i need to do this configuration again, there is an action to do this settings applied for every file created after this configuration?

  • @andrewf.lizarraga1210
    @andrewf.lizarraga1210 ปีที่แล้ว

    Thank you soooooo much

  • @trucksanddirt1506
    @trucksanddirt1506 ปีที่แล้ว

    I did that but the waveform is not changing. Output is not set.

    • @nadeemelsayed8079
      @nadeemelsayed8079 21 วันที่ผ่านมา

      You have to then run the functional simulation.

  • @gustavomuller7190
    @gustavomuller7190 ปีที่แล้ว

    Thanks!

  • @arsalanwahidqureshi6824
    @arsalanwahidqureshi6824 ปีที่แล้ว

    kiya yea honda dealer k pass hota hai main hyderabad sindh sy hu

  • @cris007671
    @cris007671 ปีที่แล้ว

    Just remove -novopt and it works.

    • @ArifMahmood
      @ArifMahmood ปีที่แล้ว

      nope it wont work, verify a thing first, otherwise u wud mislead people

    • @cris007671
      @cris007671 ปีที่แล้ว

      @@ArifMahmood You're right, I delete the -novopt the program runs only once and the problem returns in the next simulation, help me. You could type here the letters to replace, from your video I can't see if it has the "-" or if it has spaces. Thanks.

    • @cris007671
      @cris007671 ปีที่แล้ว

      @@ArifMahmood You're right, I delete the -novopt the program runs only once and the problem returns in the next simulation, help me. You could type here the letters to replace, from your video I can't see if it has the "-" or if it has spaces. Thanks.

    • @cris007671
      @cris007671 ปีที่แล้ว

      @@ArifMahmood You're right, I delete the -novopt the program runs only once and the problem returns in the next simulation, help me. You could type here the letters to replace, from your video I can't see if it has the "-" or if it has spaces. Thanks.

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    CSA SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/csa.sv CSA SV testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_csa.sv CSA VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/csa.vhd CSA VHDL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_csa.vhd

  • @Ricardo-wg3ql
    @Ricardo-wg3ql ปีที่แล้ว

    Promo*SM

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/cla.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_cla.sv VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/cla.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_cla.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/addsub_structural.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_addsub_structural.sv VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/addsub_structural.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_addsub_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/addsub.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_addsub.sv VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/addsub.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_addsub.vhd

  • @kaelrobles9932
    @kaelrobles9932 ปีที่แล้ว

    Muchas gracias mi estimado, de verdad que estuve casi 3 horas peleando con ese error y no daba con la solución de ninguna manera.

  • @魯素-t8v
    @魯素-t8v ปีที่แล้ว

    thank you , you resolve my problem

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/fa_structural.sv SV testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_fa_structural.sv VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/fa_structural.vhd VHDL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_fa_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV FA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/fa.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_fa.sv VHDL FA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/fa.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_fa.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    Instead of using this line below: " pwr=" & INTEGER'IMAGE(to_integer(unsigned'("" & power))) & Use this line below in VHDL report: " pwr=" & STD_LOGIC'IMAGE(power) & Its more proper way

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc_console.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc_console.sv VHDL PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc_console.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc_console.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc_structural.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc_structural.sv VHDL PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc_structural.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc.sv VHDL PC RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/pc.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_pc.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV SRA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sra_structural.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sra_structural.sv VHDL SRA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sra_structural.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sra_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV SRA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sra.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sra.sv VHDL SRA RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sra.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sra.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV ROR RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/ror_structural.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_ror_structural.sv VHDL ROR RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/ror_structural.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_ror_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV ROR RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/ror.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_ror.sv VHDL ROR RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/ror.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_ror.vhd

  • @mexigamplays8208
    @mexigamplays8208 ปีที่แล้ว

    tnx ur da best <3 love from Mexico

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV SLL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sll_structural.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sll_structural.sv VHDL SLL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sll_structural.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sll_structural.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SLL SV RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sll.sv SLL SV Testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sll.sv SLL VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/sll.vhd SLL VHDL Testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_sll.vhd

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    @6:11 if you dnt want to ignore this warning please see this link: th-cam.com/video/POpbr-VQBrA/w-d-xo.html

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    ROM RTL SV code: github.com/aarifboy/verilogvsvhdl/blob/main/rom_sv_input_file.sv ROM RTL SV testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_rom_input_file.sv ROM RTL VHDL code: github.com/aarifboy/verilogvsvhdl/blob/main/rom_vhdl_input_file.vhd ROM RTL VHDL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_rom_input_file.vhd Hex Input file: github.com/aarifboy/verilogvsvhdl/blob/main/test.hex

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV ROM RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/rom_sv.sv SV RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_rom.sv VHDL ROM RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/rom_vhdl.vhd VHDL RTL testbench: github.com/aarifboy/verilogvsvhdl/blob/main/test_rom.vhd

  • @jonathancampos7393
    @jonathancampos7393 ปีที่แล้ว

    Great video for lost keys

  • @ArifMahmood
    @ArifMahmood ปีที่แล้ว

    SV RTL adder code: github.com/aarifboy/verilogvsvhdl/blob/main/adder.sv VHDL RTL code: github.com/aarifboy/verilogvsvhdl/blob/main/adder.vhd