Textfile write/read using $writememh/b, $readmemh/b in verilogHDL

#verilog #vlsidesign
Verilog allows you to initialize memory from a text file with either hex or binary values: $readmemb/h("hex_memory_file. mem", memory_array, [start_address], [end_address]), it will be synthesizable.
Write into a text file with either hex or binary values: $writememb/h("hex_memory_file. mem", memory_array, [start_address], [end_address]) it will be non synthesizable.