Lab_7_Part_3: FFT IP and Verification via Testbench

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  • เผยแพร่เมื่อ 28 ส.ค. 2024
  • Topic: FFT IP and Verification via Testbench
    Instructor: Shragvi Sidharth Jha, BTech ECE, IIIT Delhi, and Saksham Gupta, BTech ECE, IIIT Delhi
    Course: ECE270: Embedded Logic Design (ELD), IIIT Delhi
    Complete playlist: • IIIT Delhi ECE270: Emb...

ความคิดเห็น • 15

  • @dakshthapar5221
    @dakshthapar5221 2 ปีที่แล้ว

    Best instructors of ELD at IIIT Delhi

  • @matzik1775
    @matzik1775 ปีที่แล้ว +1

    Hi,
    Thanks for your explications !! However, there is one thing that I don't understand. Why must we send the data in the reverse order in the test bench (from 15 to 0) ?

  • @spksv
    @spksv 11 หลายเดือนก่อน +2

    can you explain how the top_wrapper.v file changed from empty (time 4:10) to fully populated(time: 4:12)?

    • @nashatali6030
      @nashatali6030 8 หลายเดือนก่อน

      first he wrote the inputs , outputs of the module and wrote the wire data_fft, and wire out_fft
      and then to instantiate the fft_ip inside the top wrapper,
      1- he copied the instantiation template from the fft.veo file and pasted it inside the top wrapper,
      2- then he changed the port map in this instantiation template and put the inputs, outputs and wires that are declared in this top wrapper to complete the instantiation of the fft_ip.

  • @fatemeraei2369
    @fatemeraei2369 4 หลายเดือนก่อน

    excuse me my simulation when reaches to 105 ns, stops and runs forever and I can not see the output data after 0 , I use vivado 2023, and for testbench my timing scale is 1 ns/ 1 ps. can you tell me what is the issue?

    • @hassaanahmed2928
      @hassaanahmed2928 4 หลายเดือนก่อน

      I am facing same issue, did you find any solution?

  • @joelroy663
    @joelroy663 ปีที่แล้ว

    I have a doubt, I want to find the FFT of a matrix of say size 1000x64 (64 point FFT). Any sources which i can follow to create it? or is there source which has already done it?

  • @dakshthapar5221
    @dakshthapar5221 2 ปีที่แล้ว

    ECE OGs of IIITD

  • @NKODURISESHASAISRIRAMKUMAR
    @NKODURISESHASAISRIRAMKUMAR 9 หลายเดือนก่อน

    Good evening sir
    Can we implement this in HARDWARE BOARD like BASYS 3 FPGA....
    can you give some clarification on this sir pls...

  • @mujeevkhan7298
    @mujeevkhan7298 ปีที่แล้ว

    How can we detect peak frequency in the output?

  • @macaxeira82
    @macaxeira82 ปีที่แล้ว

    Greetings. Came across you video. Very helpful. One thing i don't understand is my out_data[31:0] is always Hi Z while yours is 0. My out_data never seems to change. my out_fft is just like yours and the code was also copied. any ideas?

    • @pls_vhdl
      @pls_vhdl ปีที่แล้ว

      I have the same issue, did you find a solution ?

    • @Somanath.k
      @Somanath.k ปีที่แล้ว +1

      You need to change the variables that are passed into FFT IP test bench from "s_axis_config_tdata" to the variables you declared in top wrapper "config_data"
      Same case for other variables

  • @abdelghanibourenane4221
    @abdelghanibourenane4221 9 หลายเดือนก่อน

    can you share the wrapper file code, I think you missed elaborating on that!

    • @jameswilliamson2405
      @jameswilliamson2405 2 หลายเดือนก่อน

      you can generate those with a click of a button