Half vs Full Duplex in FPGA & Tri-State Buffer Tutorial

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  • เผยแพร่เมื่อ 27 ส.ค. 2024

ความคิดเห็น • 6

  • @bamsgian9759
    @bamsgian9759 2 ปีที่แล้ว

    That's clear explaination,
    Thank you.

  • @LandBoardsLLC
    @LandBoardsLLC 5 ปีที่แล้ว +4

    SPI with a single master and single slave device is sort of full duplex, but when you have multiple SPI slaves you have the same issue with the MISO line. Each SPI device has to be tristated from the SPI until it is addressed with it's own Chip Select. So it's really not any different in design practice from I2C or any other bus where the slave transmit (to master) line has to be tristated.

    • @tariqhada4534
      @tariqhada4534 ปีที่แล้ว +1

      But i think is CS' =1 then chip will not be selected in that case doesn't matter we choose tristated buffer lines or normal ones 🤔

  • @olekristianrannekleiv762
    @olekristianrannekleiv762 3 ปีที่แล้ว

    if Rx is connected to the Tx, why do half duplex hubs need crossover cables between each other?
    it looks like half duplex only uses Tx for transmission? would it not then make sence to only use straight through cables regardless?

  • @michellenicholes2087
    @michellenicholes2087 ปีที่แล้ว

    I have a friend who says this is not correct for I2C which is an open drain system. We googled what is the difference between Tristate and open drain and it says something about current that the open drain does not allow any current. My friend says that is why the tristate does not work for I2C. Please help me understand if my friend is correct or not.

  • @karenwinchestermex
    @karenwinchestermex 5 ปีที่แล้ว

    Where's the beard? :(