I was facing lots of problems to understand fetch and execution cycle working now I understood. You are great Sir....IIT is the best because there teachers are best like you...
HALT instrcution in 8085 : In 8085 Instruction set, HLT is the mnemonic which stands for ‘Halt the microprocessor’ instruction. It is having a size of 1-Byte instruction. Using these particular instructions, as 8085 enters into the halt state, so we can put the8085 from further processing of next instructions. This is indicated by S1 and S0 control signals. During the halt, S1 and S0 output signals will become 0 0. The 8085 comes out of the Halt state when a valid interrupt occurs. In such a case, it executes the corresponding interrupt service subroutine depending upon the interrupt number and then it continues with the instruction after the HLT instruction. So it will not effectively enter into the halt state in that situation. However, in most programs, the HLT instruction is used for terminating the program. Also, activation of reset in* causes 8085 to come out of Halt state.
24:37 DOUBT!! Why it is PC8-15? It should be the higher order bytes of the address(from where we are going to READ/LOAD our data) provided in the instruction. Same goes with write cycle!!
At 46:30 Professor says that "it will set HLDA and then go to T3" But when HLDA is set, all the address and data lines are tri-stated and T&C unit gives up control over these lines. Also, as we are between T2 and T3, these lines contain the opcode read from the memory. To me it implies that we can't go to T3 after HLDA as we will lose the opcode. Can somebody clear my doubt? REPLY
why the 2clk cycles are required for fetching opcode of instructions??? Is thair exist fixed time for starting the perticular operation like eg. /wr will automatically end at the trelling edge of clk
Can anyone pls explain me How it is 3 clock cycles are needed to fetch the inst. I think only two clock cycles are needed : 1) To address the location in the main memory . 2) To read the inst from the main memory ( When inst goes to IR through data bus AD0-7
IDEOLOGY OF PHYSICS It needs many cycles to read the instruction. They have shown only two :T2 & T3. Between T2 and T3 , there are many cycles as CPU speed is fast as compared to external devices (Memory or I/O). In the state transition diagram, it's shown that many wait cycles are there.(see 44:00 )
Is this an authorized channel To use iit lectures ? It is cleary mentioned i. The officual vedio that Copying the vedio is puniahible offemse These vedios are supposes to be available In official nptel youtube channel only
At 46:30 Professor says that "it will set HLDA and then go to T3" But when HLDA is set, all the address and data lines are tri-stated and T&C unit gives up control over these lines. Also, as we are between T2 and T3, these lines contain the opcode read from the memory. To me it implies that we can't go to T3 after HLDA as we will lose the opcode. Can somebody clear my doubt?
I was facing lots of problems to understand fetch and execution cycle working now I understood. You are great Sir....IIT is the best because there teachers are best like you...
HALT instrcution in 8085 :
In 8085 Instruction set, HLT is the mnemonic which stands for ‘Halt the microprocessor’ instruction. It is having a size of 1-Byte instruction. Using these particular instructions, as 8085 enters into the halt state, so we can put the8085 from further processing of next instructions. This is indicated by S1 and S0 control signals. During the halt, S1 and S0 output signals will become 0 0.
The 8085 comes out of the Halt state when a valid interrupt occurs. In such a case, it executes the corresponding interrupt service subroutine depending upon the interrupt number and then it continues with the instruction after the HLT instruction. So it will not effectively enter into the halt state in that situation.
However, in most programs, the HLT instruction is used for terminating the program. Also, activation of reset in* causes 8085 to come out of Halt state.
thank uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu satishhhhhhhhhhhhhh
nice video for the engineering students
i like it...........
really superb....
thank u so much sir.. it is really helpful..
Hi was just wondering, doe the the architecture of 8085 applies to all other microcontroller or they have their own different architectures?
very helpful thank u sir
very helpful
24:37 DOUBT!!
Why it is PC8-15? It should be the higher order bytes of the address(from where we are going to READ/LOAD our data) provided in the instruction. Same goes with write cycle!!
At 46:30 Professor says that "it will set HLDA and then go to T3" But when HLDA is set, all the address and data lines are tri-stated and T&C unit gives up control over these lines. Also, as we are between T2 and T3, these lines contain the opcode read from the memory. To me it implies that we can't go to T3 after HLDA as we will lose the opcode. Can somebody clear my doubt?
REPLY
No the opcode is stored in IR as soon as its fetched.
Thank you so much Sir :D
sir i couldn't find low low state in two phase clock.... their are just two state according to the figure shown by you.......
why the 2clk cycles are required for fetching opcode of instructions???
Is thair exist fixed time for starting the perticular operation like
eg. /wr will automatically end at the trelling edge of clk
thanks a lots sir......
good explanation.
Why has the accumulator not been shown in the register section??
thank you so much sir.
the music at the beginning of the video, can you tell the song or any info about it
i want to know too
please replace the video very low quality sound
thank you sir
Can anyone pls explain me How it is 3 clock cycles are needed to fetch the inst.
I think only two clock cycles are needed :
1) To address the location in the main memory .
2) To read the inst from the main memory ( When inst goes to IR through data bus AD0-7
IDEOLOGY OF PHYSICS It needs many cycles to read the instruction. They have shown only two :T2 & T3. Between T2 and T3 , there are many cycles as CPU speed is fast as compared to external devices (Memory or I/O). In the state transition diagram, it's shown that many wait cycles are there.(see 44:00 )
Is this an authorized channel
To use iit lectures ?
It is cleary mentioned i. The officual vedio that
Copying the vedio is puniahible offemse
These vedios are supposes to be available
In official nptel youtube channel only
nice collection sir but if you will provide flv files instead of mp4 which can be played on vlc then no of likes will definetly rise.
thanks sir
Will this be helpful for gate exam?
there is any textbook contain those explanations?
thank you
very nice
where is the 8086 mp videos.please upload them
nice music
sir where is the low-low state in 2 phase clock ?
there r 5 low-low states in that 2 phase clock
the architecture of all the microprocessors is pretty much the same. If you compare a Micro built by Motorola, you will find the same basic structure.
Low voice
Better if louder than that
At 46:30 Professor says that "it will set HLDA and then go to T3" But when HLDA is set, all the address and data lines are tri-stated and T&C unit gives up control over these lines. Also, as we are between T2 and T3, these lines contain the opcode read from the memory. To me it implies that we can't go to T3 after HLDA as we will lose the opcode. Can somebody clear my doubt?
Akshay Sharma Oh I understood :P facepalm
+Akshay Sharma...have u understood this query?...if so pls explain me in brief.
very helpful thank u sir
very nice.