Xilinx FPGA PCIe Python Driver Development - Part 1

Python development for a Linux PCIe driver for Xilinx FPGAs. Part 1 mostly focused on ICAP features (IdCode & WBStar). This one is long as I needed to debug some issues.
Twitch: / fpga_zealot
Website: wilsoninspace.c...
Github Repo: github.com/byu...

[@badejavuade6774]

Thanks...the video is very helpful. Please can you shed more light on the architecture or block design of the Endpoint in Vivado? Do you have a video that explains it please? What Xilinx platform are you using?
Thanks

[@FPGAZealot]

I will try to review this in newer videos, but yes, older videos do go over the design a bit.

[@yigitmertsevindim1669]

Will u share education series?