Phase-Locked Loop (PLL) on an FPGA myRIO

See notes on the pll here
www.speechresea...
The the basic principle of how a phase-locked loop works along with a small amount of theory. Real demonstration of it locking and unlocking. Implemented on an FPGA system (myRIO from National Instruments). This is not a high frequency application , just a demo. Same principle applied however to any carrier frequency or FM signal.
Associate Professor Tom J.Moir [e-mail]
Source Code is here
decibel.ni.com...
Many thanks to Archie Pettigrew who taught me all I know about PLLs whilst I worked at Ampsys Electronics in Scotland.

[@2n3055]

I'm also interested in having this project files. Best Regards

[@samerguirguis9919]

Would you share your VI? Thank you