How to Write a SystemVerilog TestBench (SystemVerilog Tutorial #3)

[@idontseeit]

wow, I've been doing testbenches all wrong... the test vector is awesome!

[@FunOrange42]

i'm 2 thirds into my digital systems course and i wish i had seen this video sooner...
thanks a ton anyway

[@kikimelz4687]

I wish you slowed down a bit and explained a little bit more your thought process. I like these videos!

[@AndreaBettati]

Is the bb_b pattern some standard one for the readmem function? I expected you to specify the format at somepoint but you did not so I guess this is just the way readmem works.
Thanks for the vid! Need more of this on youtube

[@lesstor99]

the underscore (_) is ignored by readmemb and readmemh in verilog
it is used to enhance readability

[@wallerstc]

nice series

[@galmagen7696]

grate series