SystemVerilog for Hardware Synthesis

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  • เผยแพร่เมื่อ 2 ม.ค. 2025

ความคิดเห็น • 8

  • @sourabhtapas
    @sourabhtapas 5 ปีที่แล้ว

    Very precise and relevant use of technical words in explaination. Less scope for confusion. Thanks for sharing.

  • @duret-robertlouis2973
    @duret-robertlouis2973 4 ปีที่แล้ว

    Great video ! Clear and well paced. Thank you very much !

  • @nikhilkale1878
    @nikhilkale1878 8 ปีที่แล้ว

    very helpful... Thanks:) ... Can you upload one video teaching all the constructs?

  • @danielorlando8787
    @danielorlando8787 11 ปีที่แล้ว

    very interesting, great contribution

  • @iwua37
    @iwua37 6 ปีที่แล้ว

    what does 1'b1 means at 17:45? thanks

    • @chrisslott
      @chrisslott 6 ปีที่แล้ว +4

      Just in case your question is still unanswered -
      1'b1 is a format specified numeric with these rules:
      1 is the size, 1-bit
      ' is the apostrophe
      b is the type, binary
      1 is the value, which is 1
      So, it means "A 1-bit, binary number, that is the value 1"
      Another example would be 4'b0101 (4-bits specified in binary) or 16'd255 (16-bits specified in decimal).
      The case statement…
      unique case (1'b1)
      state[0]: f = 0;
      state[1]: f = 1;
      state[2]: f = 2;
      state[3]: f = 3;
      endcase
      …means "case (binary 1)" to match against a binary 1 instead of decimal 1.
      It's done this way because state is a 4-bit vector defined as `input [3:0] state` above. Since it's 4-bits, each index is either on or off - 1 or 0 binary.
      We're just checking if each state index is on or off, the binary 1 or 0. If a state's value is 1 it matches the case and executed.
      I didn't mean to over-explain, I just wanted anyone to be able to read this and understand. I hope that helps!

  • @swethajan
    @swethajan 11 ปีที่แล้ว

    Thank You Sir! Helped a lot! :)