I comment just in very special occasions and I need to do it on this one! Thank you sir for one of the clearest explanations that I've encountered in electronics. This has given me the will to keep pushing on this subject!
Just wanted to say thank you. I struggled with this concept in college and now I have a much better understanding because of your video which not only has a great visual/explanation but also allows me to rewind as many times as I need to
Thank you sir! This is a great series for all level of audience to understand the thoery of RAM and etc.. There must be plenty of efforts and deep understanding.
Your videos are some of the best videos I have seen that explain computer science concepts so clearly. Keep creating this content, and thank you very much.
THANK YOU! SIR! I'm only through second video of your DRAM series, but I'm already sure that this is a masterpiece from some expert in the industry. The effort you put in this series is astonishing, such detailed illustration animated, such accurate explanation well rehearsed. You clear a dark cloud hung over my head for days! You are a life saver! May I ask, do you have a team for this work ? Also, is there a paid course I can buy ?
Thank you SOOO much. Saved my day. The series of vids about DRAM you made is so well explained. Also, there is a minor mistake which in 10:04 the “Data out” line should be “Data input” if I understands correctly.
What determines for how long the Word-Line will be active? At first I thought for as long as RAS is enabled and I concluded that disabling RAS would have to occur after writing back the row. Your explanation suggests otherwise - are there latches in the row decoder? Or is the Word-Line simply afloat in hope that its charge will remain for the duration of the operation? Asides from that, this is the most comprehensive yet simple explanation the internet has on offer. Thanks! :)
Good question. Most RAM sticks come with timing information. You will see numbers quoted like 16-18-18-38. I plan to make a video about these one day. In the meantime, search in Google for 'RAM timings'. :)KD
A bit of a glib answer for now I'm afraid. The row buffer is comprised of a set of sense amplifiers. These are signal detectors/amplifiers with built in latches. The are constructed and connected in such a was as to allow a single latched value to the read, or changed, without affecting the others. The details of sense amps was something I decided no to go into (yet). :)KD
Hi Sir, Thank you for the nice lectures and for preparing beautiful slides. I know you have worked hard in preparing slides, if possible, can I get your slides. I will explain my students, with your reference. Thank you
i can't get the read and write diagram in the video if we active RAS and CAS at a shared time then both ROW and COL address buffer will be write at the shared time can you explain this to me? 🙏
Such a masterpiece video on DRAM No one will explain this much clearly You are superb sir Sir, at 7:07 whenever RAS is disabled , by doing so we cannot deassert word line right? So at 7:23, then how to deassert word line?
for qn 7:23, a decoder can have an enbale pin(a decoder has and gate at its output stages, so an enable pin is anded with all gates. So if enable is low, then all wordlines are deasserted)
Some books show that the data bus is connected on top of the matrix representation, that would imply that all the bits stored in the bottom half of the matrix under the sense amplifier get inverted before reaching the data bus. Is that correct?
@8:36 why isn't the row address strobe set to high when column address strobe is set to low? Wouldn't we be activating the wrong row (and thus messing with the sense amplifier inputs)?
8:22 if the address is for the column decoder but both the ras and cas are applied, wouldn't that also update the data in the row address buffer? Wouldn't that cause us to select a row different from the intended one?
Did I miss it? You mentioned that the read is destructive, but I didn't catch how the existing bits were put back into the selected column? Also, is that what a "refresh cycle" is?
Sir, why is the word line deasserted (which I guess means set to low) when writing back to the DRAM? Don't the transistors need to have their gates on (set to high) to write (pass current) through them to the capacitors?
I bet in reading the row of cells, the charges that go to the 0 bit cells must come from the other cells that are bit 1 and not from bit line. Who knows? But how it is detected that a particular cell is discharged since the whole row is read. There are no sensors in each cell, is there? The gates of the whole row is receiving voltage and the transistor is open.
No this is not required for most A level courses, certainly not OCR or AQA. I do nevertheless touch on this with my own A level students because it explains why accessing a data item in an array variable, by means of an index number (which equates to a memory address), takes the same amount of time no matter where the item is. When I started making this series, I became curious and carried on. :)KD
Hello sir, why is there are a need for a "precharge" of half of the voltage? It was mentioned in video 1 but I'm still confused. I get that when precharging, the gate(row address) is turned off but ALL the bit lines are charged to half the voltage. But I don't get "why" is there a need for precharging before read/write, it seems to me that we can still read/write even without precharging the bitlines first......
Lets take a look at one cell just to make it easier. You precharge to 1.5V because all you care about whether the capacitor is charging or discharging. You start at 1.5 Voltages because it is makes the read/write speeds faster since it's right in the middle. You don't need to completely charge or discharge the capacitors in order for the sensing circuit to know if the cell is a '1' or a '0'. Instead you look at the general trends. However, if there is no precharge, then it will take more time to read and write the cell because instead of going from 1.5V to 3V for a logic high, you will have to go from 0V to 3V to get a '1'. For example: For reading, if the sensing circuit reads 1.49V the capacitor is charging from 0V meaning the cell is at a logic level '0'. If the sensing circuit reads 1.51V then the circuit is a logic is discharging from 3V making it a logic '1'.
Amazing !
Amazing !
Amazing !
Please more videos.
Thank you :)KD
Wow, This is one of the clearest videos on any subject I've ever watched, Thanks tons!
You are most welcome :)KD
Best video on TH-cam explaining DRAM. Thanks!
Thank you :)KD
I comment just in very special occasions and I need to do it on this one! Thank you sir for one of the clearest explanations that I've encountered in electronics. This has given me the will to keep pushing on this subject!
Thank you so much for the lovely comment. That's one of the things that keeps me doing this. :)KD
This is an excellent lecture. Really helped me , a non-EE background person, to understand DRAM operation
You are most welcome :)KD
I've watched a lot of videos that talk about DRAM, yours are without a doubt the best. please keep making more videos!
Just wanted to say thank you. I struggled with this concept in college and now I have a much better understanding because of your video which not only has a great visual/explanation but also allows me to rewind as many times as I need to
You are very welcome. Delighted to help :)KD
Thank you sir! This is a great series for all level of audience to understand the thoery of RAM and etc.. There must be plenty of efforts and deep understanding.
You're very welcome :)KD
Your videos are some of the best videos I have seen that explain computer science concepts so clearly. Keep creating this content, and thank you very much.
Thank you. I've got a few ideas on the drawing board :)KD
Best DRAM tutorial in internet man...
:) KD
vow vow vow just amazing, crystal clear explanation !!!
Thank you :)KD
Good explanation, now I feel smarter than ten minutes ago.
lmao
Super helpful for my computer architecture class at UCR, thanks for making this series
This guy deserves the Turing Award
Now that's what I call a compliment! Thank you :)KD
THANK YOU! SIR!
I'm only through second video of your DRAM series, but I'm already sure that this is a masterpiece from some expert in the industry. The effort you put in this series is astonishing, such detailed illustration animated, such accurate explanation well rehearsed.
You clear a dark cloud hung over my head for days! You are a life saver!
May I ask, do you have a team for this work ? Also, is there a paid course I can buy ?
Thank you so much for your kind comments. No team; just me. I don't make paid content, I want to keep it free for now. :)KD
@@ComputerScienceLessons producing such high quality content and insisting on keeping it free, you're a beautiful human being. Thank you so much!
@@ComputerScienceLessons do you have a website? Paid content?
Thank you SOOO much. Saved my day.
The series of vids about DRAM you made is so well explained.
Also, there is a minor mistake which in 10:04 the “Data out” line should be “Data input” if I understands correctly.
Thanks a lot sir for the amazing exaplanation and crystal clear concept
You're most welcome :)KD
very high-quality content. Thank you!
Thank you :)KD
Thanks for spreading knowledge.
You're most welcome. Thanks for the acknowledgement. :)KD
SO GOOOOOOOOOOOOOOOOOOOOOOOOOOOD!!!
Thank you soooooooo much :)KD
You are a legend
Thank you very much
You're very welcome :)KD
this is so good :)
Thanks for your help. It's very useful.
Thank you - you're very welcome :)KD
Really an amazing details. I can vouch for the concurrence of the details to the present-day arch being a Server HW developer
Thank you :)KD
Thank you Sir! Excellent explanation!
What determines for how long the Word-Line will be active? At first I thought for as long as RAS is enabled and I concluded that disabling RAS would have to occur after writing back the row. Your explanation suggests otherwise - are there latches in the row decoder? Or is the Word-Line simply afloat in hope that its charge will remain for the duration of the operation?
Asides from that, this is the most comprehensive yet simple explanation the internet has on offer. Thanks! :)
Good question. Most RAM sticks come with timing information. You will see numbers quoted like 16-18-18-38. I plan to make a video about these one day. In the meantime, search in Google for 'RAM timings'. :)KD
Great video! You already use precharge, so I think it would be useful if you introduced the "Activate" command terminology as appropriate, too.
Good point - thanks. I'll be doing some videos on Flash memory soon and can bring in some new terminology. :)KD
PERFECT VIDEO!!!!!
Thank you :)KD
beautiful explanation thank you
You are very welcome. Thanks for the lovely comment. :)KD
very useful! i like you teacher
8:24 what prevents column address to mess up the row buffer when CAS is enabled ?
A bit of a glib answer for now I'm afraid. The row buffer is comprised of a set of sense amplifiers. These are signal detectors/amplifiers with built in latches. The are constructed and connected in such a was as to allow a single latched value to the read, or changed, without affecting the others. The details of sense amps was something I decided no to go into (yet). :)KD
Thanks
Thanks, this is great.
Helpfull
Hi Sir, Thank you for the nice lectures and for preparing beautiful slides. I know you have worked hard in preparing slides, if possible, can I get your slides. I will explain my students, with your reference. Thank you
i can't get the read and write diagram in the video if we active RAS and CAS at a shared time then both ROW and COL address buffer will be write at the shared time can you explain this to me? 🙏
awesome
Such a masterpiece video on DRAM
No one will explain this much clearly
You are superb sir
Sir, at 7:07 whenever RAS is disabled , by doing so we cannot deassert word line right?
So at 7:23, then how to deassert word line?
even i have same dout
for qn 7:23, a decoder can have an enbale pin(a decoder has and gate at its output stages, so an enable pin is anded with all gates. So if enable is low, then all wordlines are deasserted)
Some books show that the data bus is connected on top of the matrix representation, that would imply that all the bits stored in the bottom half of the matrix under the sense amplifier get inverted before reaching the data bus. Is that correct?
@8:36 why isn't the row address strobe set to high when column address strobe is set to low? Wouldn't we be activating the wrong row (and thus messing with the sense amplifier inputs)?
8:22 if the address is for the column decoder but both the ras and cas are applied, wouldn't that also update the data in the row address buffer? Wouldn't that cause us to select a row different from the intended one?
Did I miss it? You mentioned that the read is destructive, but I didn't catch how the existing bits were put back into the selected column? Also, is that what a "refresh cycle" is?
Nevermind.. if anyone else missed this too - It's in the first video of the series. I had stumbled upon this one first!
Sir, why is the word line deasserted (which I guess means set to low) when writing back to the DRAM? Don't the transistors need to have their gates on (set to high) to write (pass current) through them to the capacitors?
Thanks 1:27
YW :)KD
Request you to make a video on LPDDR5.
I'll look into it :)KD
this is very complicated ..
I bet in reading the row of cells, the charges that go to the 0 bit cells must come from the other cells that are bit 1 and not from bit line. Who knows? But how it is detected that a particular cell is discharged since the whole row is read. There are no sensors in each cell, is there? The gates of the whole row is receiving voltage and the transistor is open.
in 6:45 is it necessary that when CAS is 0 the RAS should be 1 ?
Is this for A level? If so which examining board would it fall in?
No this is not required for most A level courses, certainly not OCR or AQA. I do nevertheless touch on this with my own A level students because it explains why accessing a data item in an array variable, by means of an index number (which equates to a memory address), takes the same amount of time no matter where the item is. When I started making this series, I became curious and carried on. :)KD
why need a 6 line address bus on 8x8 array of cells (64 cells) curios how you come up with 6 line address bus
I just wanted to illustrate the principle but keep the diagram simple. Yes, we normally work in powers of 2. :)KD
Hello sir, why is there are a need for a "precharge" of half of the voltage? It was mentioned in video 1 but I'm still confused. I get that when precharging, the gate(row address) is turned off but ALL the bit lines are charged to half the voltage. But I don't get "why" is there a need for precharging before read/write, it seems to me that we can still read/write even without precharging the bitlines first......
Lets take a look at one cell just to make it easier. You precharge to 1.5V because all you care about whether the capacitor is charging or discharging. You start at 1.5 Voltages because it is makes the read/write speeds faster since it's right in the middle. You don't need to completely charge or discharge the capacitors in order for the sensing circuit to know if the cell is a '1' or a '0'. Instead you look at the general trends.
However, if there is no precharge, then it will take more time to read and write the cell because instead of going from 1.5V to 3V for a logic high, you will have to go from 0V to 3V to get a '1'.
For example: For reading, if the sensing circuit reads 1.49V the capacitor is charging from 0V meaning the cell is at a logic level '0'. If the sensing circuit reads 1.51V then the circuit is a logic is discharging from 3V making it a logic '1'.
Dram sono sostituibili con altre? Grazie
🥰
🐱👤 :)KD
@ 2:00, 8 binary states in a 3 row bus are:
111
110
011
101
100
010
001
000
I'm not sure why I have to spend more than $20,000 per semester to attend university after watching your video🥹
In my country, India we even don't know practically the basics of high school 😢
¡Gracias!
You're welcome :)KD
i really like your timing diagram explanation
Unbelievably high quality video, thank you for this!!
Thank you, and you are very welcome :)KD
concise and useful ! thanks
You're welcome :)KD